WorldCat Identities

Nicolau, Alexandru

Overview
Works: 102 works in 182 publications in 1 language and 2,048 library holdings
Genres: Conference papers and proceedings 
Roles: Editor, Author
Classifications: QA76.58, 005.453
Publication Timeline
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Most widely held works by Alexandru Nicolau
Memory architecture exploration for programmable embedded systems by Peter Grun( )

16 editions published between 2002 and 2011 in English and held by 416 WorldCat member libraries worldwide

Memory Architecture Exploration for Programmable Embedded Systems addresses efficient exploration of alternative memory architectures, assisted by a "compiler-in-the-loop" that allows effective matching of the target application to the processor-memory architecture. This new approach for memory architecture exploration replaces the traditional black-box view of the memory system and allows for aggressive co-optimization of the programmable processor together with a customized memory system. The book concludes with a set of experiments demonstrating the utility of this exploration approach. The authors perform architecture and compiler exploration for a set of large, real-life benchmarks, uncovering promising memory configurations from different perspectives, such as cost, performance and power
Languages and compilers for parallel computing by LCPC (Workshop)( Book )

10 editions published between 1989 and 1995 in English and held by 253 WorldCat member libraries worldwide

A collection of papers examining the languages and compilers for parallel computing. It covers a wide variety of topics, ranging from improving parallel program performance using critical path analysis, to software engineering of parallel programs in the computation-orientated display environment
IWIA 2005 : Innovative architecture for future generation high-performance processors and systems by International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems( )

5 editions published between 2005 and 2006 in English and held by 226 WorldCat member libraries worldwide

Advances in languages and compilers for parallel processing by Alexandru Nicolau( Book )

11 editions published in 1991 in English and held by 221 WorldCat member libraries worldwide

Mathematics of Computing -- Parallelism
Memory issues in embedded systems-on-chip : optimizations and exploration by Preeti Ranjan Panda( Book )

9 editions published in 1999 in English and held by 183 WorldCat member libraries worldwide

Memory Issues in Embedded Systems-On-Chip: Optimizations and Explorations is designed for different groups in the embedded systems-on-chip arena. First, it is designed for researchers and graduate students who wish to understand the research issues involved in memory system optimization and exploration for embedded systems-on-chip. Second, it is intended for designers of embedded systems who are migrating from a traditional micro-controllers centered, board-based design methodology to newer design methodologies using IP blocks for processor-core-based embedded systems-on-chip. Also, since Memory Issues in Embedded Systems-on-Chip: Optimization and Explorations illustrates a methodology for optimizing and exploring the memory configuration of embedded systems-on-chip, it is intended for managers and system designers who may be interested in the emerging capabilities of embedded systems-on-chip design methodologies for memory-intensive applications
Languages and compilers for parallel computing : 7th International Workshop, Ithaca, NY, USA, August 8-10, 1994 : proceedings by David Sehr( )

3 editions published between 1995 and 1997 in English and held by 160 WorldCat member libraries worldwide

This volume presents revised versions of the 32 papers accepted for the Seventh Annual Workshop on Languages and Compilers for Parallel Computing, held in Ithaca, NY in August 1994. The 32 papers presented report on the leading research activities in languages and compilers for parallel computing and thus reflect the state of the art in the field. The volume is organized in sections on fine-grain parallelism, align- ment and distribution, postlinear loop transformation, parallel structures, program analysis, computer communication, automatic parallelization, languages for parallelism, scheduling and program optimization, and program evaluation
LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING : 8th International Workshop, LCPC '95 Columbus, Ohio, USA, August 1995 Proceedings by C.-H Huang( )

3 editions published in 1996 in English and held by 131 WorldCat member libraries worldwide

Annotation This book presents the refereed proceedings of the Eighth Annual Workshop on Languages and Compilers for Parallel Computing, held in Columbus, Ohio in August 1995. The 38 full revised papers presented were carefully selected for inclusion in the proceedings and reflect the state of the art of research and advanced applications in parallel languages, restructuring compilers, and runtime systems. The papers are organized in sections on fine-grain parallelism, interprocedural analysis, program analysis, Fortran 90 and HPF, loop parallelization for HPF compilers, tools and libraries, loop-level optimization, automatic data distribution, compiler models, irregular computation, object-oriented and functional parallelism
Parallel language and compiler research in Japan by Lubomir Bic( Book )

6 editions published in 1995 in English and held by 126 WorldCat member libraries worldwide

Parallel Language and Compiler Research in Japan offers the international community an opportunity to learn in-depth about key Japanese research efforts in the particular software domains of parallel programming and parallelizing compilers. These are important topics that strongly bear on the effectiveness and affordability of high performance computing systems. The chapters of this book convey a comprehensive and current depiction of leading edge research efforts in Japan that focus on parallel software design, development, and optimization that could be obtained only through direct and personal interaction with the researchers themselves
Concurrent information processing and computing by NATO Advanced Research Workshop on Concurrent information processing and computing( Book )

5 editions published in 2005 in English and held by 65 WorldCat member libraries worldwide

Languages and Compilers for Parallel Computing by Utpal Banerjee( )

1 edition published in 1993 in English and held by 34 WorldCat member libraries worldwide

Annotation The articles in this volume are revised versions of the bestpapers presented at the Fifth Workshop on Languages andCompilers for Parallel Computing, held at Yale University, August 1992. The previous workshops in this series were heldin Santa Clara (1991), Irvine (1990), Urbana (1989), andIthaca (1988). As in previous years, a reasonablecross-section of some of the best work in the field ispresented. The volume contains 35 papers, mostly by authorsworking in the U.S. or Canada but also by authors fromAustria, Denmark, Israel, Italy, Japan and the U.K
Languages and Compilers for Parallel Computing : 8th International Workshop, LCPC '95 Columbus, Ohio, USA, August 10-12, 1995 Proceeding by C.-H Huang( )

1 edition published in 1996 in English and held by 32 WorldCat member libraries worldwide

PPoPP'13 proceedings of the 2013 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming; February 23-27, 2013, Shenzhen, China by ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming( )

2 editions published in 2013 in English and held by 25 WorldCat member libraries worldwide

SPARK : a parallelizing approach to the high-level synthesis of digital circuits by Sumit Gupta( )

4 editions published in 2004 in English and held by 21 WorldCat member libraries worldwide

Rapid advances in microelectronic integration and the advent of Systems-on-Chip have fueled the need for high-level synthesis, i.e., an automated approach to the synthesis of hardware from behavioral descriptions. SPARK: A Parallelizing Approach to the High - Level Synthesis of Digital Circuits presents a novel approach to the high-level synthesis of digital circuits -- that of parallelizing high-level synthesis (PHLS). This approach uses aggressive code parallelizing and code motion techniques to discover circuit optimization opportunities beyond what is possible with traditional high-level synthesis. This PHLS approach addresses the problems of the poor quality of synthesis results and the lack of controllability over the transformations applied during the high-level synthesis of system descriptions with complex control flows, that is, with nested conditionals and loops. Also described are speculative code motion techniques and dynamic compiler transformations that optimize the circuit quality in terms of cycle time, circuit size and interconnect costs. We describe the SPARK parallelizing high-level synthesis framework in which we have implemented these techniques and demonstrate the utility of SPARK's PHLS approach using designs derived from multimedia and image processing applications. We also present a case study of an instruction length decoder derived from the Intel Pentium-class of microprocessors. This case study serves as an example of a typical microprocessor functional block with complex control flow and demonstrates how our techniques are useful for such designs. SPARK: A Parallelizing Approach to the High - Level Synthesis of Digital Circuits is targeted mainly to embedded system designers and researchers. This includes people working on design and design automation. The book is useful for researchers and design automation engineers who wish to understand how the main problems hindering the adoption of high-level synthesis among designers
Languages and compilers for parallel computing : 5th international workshop, New Haven, Connecticut, USA, August 3-5, 1992 : proceedings by Utpal Banerjee( )

1 edition published in 1993 in English and held by 15 WorldCat member libraries worldwide

The articles in this volume are revised versions of the best papers presented at the Fifth Workshop on Languages and Compilers for Parallel Computing, held at Yale University, August 1992. The previous workshops in this series were held in Santa Clara (1991), Irvine (1990), Urbana (1989), and Ithaca (1988). As in previous years, a reasonable cross-section of some of the best work in the field is presented. The volume contains 35 papers, mostly by authors working in the U.S. or Canada but also by authors from Austria, Denmark, Israel, Italy, Japan and the U.K
Microflow : a fine-grain parallel processing approach by Jon Solworth( Book )

3 editions published between 1985 and 1986 in English and held by 8 WorldCat member libraries worldwide

ABSTRACT NOT SUPPLIED
Adaptive bitonic sorting : an optimal parallel algorithm for shared memory machines by G Bilardi( Book )

3 editions published in 1986 in English and held by 5 WorldCat member libraries worldwide

We propose a parallel algorithm, called adaptive bitonic sorting, which runs on a PRAC, a shared-memory multiprocessor where fetch and store conflicts are disallowed. On a $P$ processors PRAC, our algorithm achieves optimal performance $TP = O(N \log N)$, for any computation time $T$ in the range $\Omega (\log[superscript]{2} N) \leq T \leq O(N \log N)$. Adaptive bitonic sorting has also a small constant factor, since it performs less than $2N \log N$ comparisons, and only a handful of operations per comparison
Static scheduling for dynamic dataflow machines by Micah Beck( Book )

2 editions published in 1990 in English and held by 5 WorldCat member libraries worldwide

These analyses permit the compiler to allocate resources according to expected patterns of usage, thus reducing overall resource requirements. Finally, we show how our schema can be implemented on the Monsoon dataflow machine being built at M.I.T."
A fine-grain parallelizing compiler by Alexandru Nicolau( Book )

2 editions published in 1986 in English and held by 4 WorldCat member libraries worldwide

Percolation Scheduling (PS) is a new technique for compiling programs into parallel code. It attempts to overcome problems that limit the effectiveness and applicability of currently available techniques
A development environment for scientific parallel programs by Alexandru Nicolau( Book )

1 edition published in 1985 in English and held by 4 WorldCat member libraries worldwide

ROPE : a new twist in computer architectures by Kevin Karplus( Book )

2 editions published in 1987 in English and held by 4 WorldCat member libraries worldwide

Supercomputer architectures are not as fast as logic technology allows because memories are slow than the CPU, conditional jumps limit the usefulness of pipelining and prefetching mechanisms, and functional-unit parallelism is limited by the speed of hardware scheduling. We propose a supercomputer architecture called Ring Of Prefetch Elements (ROPE) that attempts to solve the problems of memory latency and conditional jumps without hardware scheduling. ROPE consists of a pipelined CPU or very-large-instruction-word data path with a new instruction prefetching mechanism that supports general multi-way conditional jumps. To get high-performance without scheduling hardware, ROPE relies on an optimizing compiler based on a global code transformation technique (Percolation Scheduling). This paper describes both the promise and the limitations of ROPE
 
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Memory architecture exploration for programmable embedded systems
Covers
Languages and compilers for parallel computingMemory issues in embedded systems-on-chip : optimizations and explorationLanguages and compilers for parallel computing : 7th International Workshop, Ithaca, NY, USA, August 8-10, 1994 : proceedingsLANGUAGES AND COMPILERS FOR PARALLEL COMPUTING : 8th International Workshop, LCPC '95 Columbus, Ohio, USA, August 1995 ProceedingsParallel language and compiler research in JapanConcurrent information processing and computingLanguages and Compilers for Parallel ComputingSPARK : a parallelizing approach to the high-level synthesis of digital circuitsLanguages and compilers for parallel computing : 5th international workshop, New Haven, Connecticut, USA, August 3-5, 1992 : proceedings
Alternative Names
Nicolau, A.

Nicolau, Alex.

Languages
English (90)