WorldCat Identities

Monteiro, José 1966-

Overview
Works: 9 works in 39 publications in 1 language and 779 library holdings
Genres: Conference papers and proceedings 
Roles: Author, Editor, htt
Classifications: TK7868.L6, 621.395
Publication Timeline
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Most widely held works by José Monteiro
Integrated circuit and system design : power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 : revised selected papers by José Monteiro( )

10 editions published between 2009 and 2010 in English and held by 371 WorldCat member libraries worldwide

"This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008." "The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures."--Back cover
Computer-aided design techniques for low power sequential logic circuits by José Monteiro( Book )

10 editions published between 1996 and 1997 in English and held by 184 WorldCat member libraries worldwide

Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital system determines its heat dissipation as well as battery life. For some systems, power has become the most critical design constraint. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits presents a methodology for low power design. The authors first present a survey of techniques for estimating the average power dissipation of a logic circuit. At the logic level, power dissipation is directly related to average switching activity. A symbolic simulation method that accurately computes the average switching activity in logic circuits is then described. This method is extended to handle sequential logic circuits by modeling correlation in time and by calculating the probabilities of present state lines. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits then presents a survey of methods to optimize logic circuits for low power dissipation which target reduced switching activity. A method to retime a sequential logic circuit where registers are repositioned such that the overall glitching in the circuit is minimized is also described. The authors then detail a powerful optimization method that is based on selectively precomputing the output logic values of a circuit one clock cycle before they are required, and using the precomputed value to reduce internal switching activity in the succeeding clock cycle. Presented next is a survey of methods that reduce switching activity in circuits described at the register-transfer and behavioral levels. Also described is a scheduling algorithm that reduces power dissipation by maximising the inactivity period of the modules in a given circuit. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits concludes with a summary and directions for future research
VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things : 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23–25, 2017, Revised and Extended Selected Papers by IFIP/IEEE International Conference on Very Large Scale Integration( )

5 editions published in 2019 in English and held by 138 WorldCat member libraries worldwide

This book contains extended and revised versions of the best papers presented at the 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, held in Abu Dhabi, United Arab Emirates, in August 2017. The 11 papers included in this book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the latest scientific and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) Design. On the occasion of the silver jubilee of the VLSI-SoC conference series the book also includes a special chapter that presents the history of the VLSI-SoC series of conferences and its relation with VLSI-SoC evolution since the early 80s up to the present
Integrated circuit and system design : power and timing modeling, optimization and simulation ; 18th international workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. proceedings by David Hutchison( )

5 editions published in 2009 in English and held by 57 WorldCat member libraries worldwide

This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures
Computer architecture : digital circuits to microprocessors by Guilherme Arroz( Book )

4 editions published between 2018 and 2019 in English and held by 22 WorldCat member libraries worldwide

Computer-aided design techniques for low power sequential logic circuits by José Monteiro( Book )

1 edition published in 1997 in English and held by 3 WorldCat member libraries worldwide

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers by Lars Svensson( )

2 editions published in 2009 in English and held by 3 WorldCat member libraries worldwide

This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures
Integrated circuit and system design : power and timing modeling, optimization and simulation : revised selected papers by Optimization and Simulation Power and Timing Modeling( Book )

1 edition published in 2010 in English and held by 1 WorldCat member library worldwide

 
Audience Level
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Audience Level
1
  Kids General Special  
Audience level: 0.60 (from 0.52 for Integrated ... to 1.00 for Integrated ...)

Integrated circuit and system design : power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 : revised selected papers Integrated circuit and system design : power and timing modeling, optimization and simulation ; 18th international workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. proceedings
Covers
Computer-aided design techniques for low power sequential logic circuitsIntegrated circuit and system design : power and timing modeling, optimization and simulation ; 18th international workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. proceedingsComputer-aided design techniques for low power sequential logic circuitsIntegrated circuit and system design : power and timing modeling, optimization and simulation : revised selected papers
Alternative Names
Monteiro, José Carlos.

Monteiro, José Carlos 1966-

Languages
English (39)