WorldCat Identities

O'Connor, Ian

Works: 55 works in 91 publications in 3 languages and 885 library holdings
Roles: Other, Author, Editor, Thesis advisor, Opponent, Publishing director, htt
Publication Timeline
Most widely held works by Ian O'Connor
Design technology for heterogeneous embedded systems by G Nicolescu( )

15 editions published between 2011 and 2012 in English and held by 400 WorldCat member libraries worldwide

Design technology to address the new and vast problem of heterogeneous embedded systems design while remaining compatible with standard 'More Moore' flows, i.e. capable of simultaneously handling both silicon complexity and system complexity, represents one of the most important challenges facing the semiconductor industry today and will be for several years to come. While the micro-electronics industry, over the years and with its spectacular and unique evolution, has built its own specific design methods to focus mainly on the management of complexity through the establishment of abstraction
Integrated optical interconnect architectures for embedded systems by Ian O'Connor( )

12 editions published in 2013 in English and German and held by 394 WorldCat member libraries worldwide

This book provides a broad overview of current research in optical interconnect technologies and architectures. Introductory chapters on high-performance computing and the associated issues in conventional interconnect architectures, and on the fundamental building blocks for integrated optical interconnect, provide the foundations for the bulk of the book which brings together leading experts in the field of optical interconnect architectures for data communication. Particular emphasis is given to the ways in which the photonic components are assembled into architectures to address the needs of data-intensive on-chip communication, and to the performance evaluation of such architectures for specific applications. Provides state-of-the-art research on the use of optical interconnects in Embedded Systems; Begins with coverage of the basics for high-performance computing and optical interconnect; Includes a variety of on-chip optical communication topologies; Features coverage of system integration and optically-enhanced MPSoC performance; Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings
Design Technology for Heterogeneous Embedded Systems( )

1 edition published in 2012 in English and held by 11 WorldCat member libraries worldwide

Designing technology to address the problem of heterogeneous embedded systems, while remaining compatible with standard “More Moore” flows, i.e. capable of handling simultaneously both silicon complexity and system complexity, represents one of the most important challenges facing the semiconductor industry today. While the micro-electronics industry has built its own specific design methods to focus mainly on the management of complexity through the establishment of abstraction levels, the emergence of device heterogeneity requires new approaches enabling the satisfactory design of physically heterogeneous embedded systems for the widespread deployment of such systems. This book, compiled largely from a set of contributions from participants of past editions of the Winter School on Heterogeneous Embedded Systems Design Technology (FETCH), proposes a broad and holistic overview of design techniques used to tackle the various facets of heterogeneity in terms of technology and opportunities at the physical level, signal representations and different abstraction levels, architectures and components based on hardware and software, in all the main phases of design (modeling, validation with multiple models of computation, synthesis and optimization). It concentrates on the specific issues at the interfaces, and is divided into two main parts. The first part examines mainly theoretical issues and focuses on the modeling, validation and design techniques themselves. The second part illustrates the use of these methods in various design contexts at the forefront of new technology and architectural developments
Méthodologies de conception ASIC pour des systèmes sur puce 3D hétérogènes à base de réseaux sur puce 3D by Mohamad Jabbar( )

2 editions published in 2013 in French and English and held by 3 WorldCat member libraries worldwide

In this thesis, we study the exploration 3D NoC architectures through physical design implementations using real 3D technology used in the industry. Based on the proposed 3D design flow focusing on timing verification by leveraging the benefit of negligible delay of microbumps structure for vertical connections, we have conducted partitioning techniques for 3D NoC-based MPSoC architecture including homogeneous and heterogeneous stacking using Tezzaron 3D IC technlogy. Design and implementation trade-off in both partitioning methods is investigated to have better insight about 3D architecture so that it can be exploited for optimal performance. Using homogeneous 3D stacking approach, NoC architectures are explored to identify the best topology between 2D and 3D topology for 3D MPSoC implementation. The architectural explorations have also considered different process technologies highlighting the wire delay effect to the 3D architecture performance especially for interconnect-dominated design. Additionally, we performed heterogeneous 3D stacking of NoC-based MPSoC implementation with GALS style approach and presented several physical designs related analyses regarding 3D MPSoC design and implementation using 2D EDA tools. Finally we conducted an exploration of 2D EDA tool on different 3D architecture to evaluate the impact of 2D EDA tools on the 3D architecture performance. Since there is no commercialize 3D design tool until now, the experiment is important on the basis that designing 3D architecture using 2D EDA tools does not have a strong and direct impact to the 3D architecture performance mainly because the tools is dedicated for 2D architecture design
Neurone analogique robuste et technologies émergentes pour les architectures neuromorphiques by Antoine Joubert( )

1 edition published in 2013 in French and held by 2 WorldCat member libraries worldwide

Due to the latest evolutions in microelectronic field, a special care has to be given to circuit designs. In aggressive technology nodes down to dozen of nanometres, a recent need of high energy efficiency has emerged. Consequently designers are currently exploring heterogeneous multi-cores architectures based on accelerators. Besides this problem, variability has also become a major issue. It is hard to maintain a specification without using an overhead in term of surface and/or power consumption. Therefore accelerators should be robust against fabrication defects. Neuromorphic architectures, especially spiking neural networks, address robustness and power issues by their massively parallel and hybrid computation scheme. As they are able to tackle a broad scope of applications, they are good candidates for next generation accelerators. This PhD thesis will present two main aspects. Our first and foremost objectives were to specify and design a robust analog neuron for computational purposes. It was designed and simulated in a 65 nm process. Used as a mathematical operator, the neuron was afterwards integrated in two versatile neuromorphic architectures. The first circuit has been characterized and performed some basic computational operators. The second part explores the impact of emerging devices in future neuromorphic architectures. The starting point was a study of the scalability of the neuron in advanced technology nodes ; this approach was then extended to several technologies such as Through-Silicon-Vias or resistive memories
Contrôle des performances et conciliation d'erreurs dans les décodeurs d'image by Ghislain Takam tchendjou( )

1 edition published in 2018 in French and held by 2 WorldCat member libraries worldwide

Cette thèse porte sur le développement et l'implémentation des algorithmes de détection et de correction des erreurs dans les images, en vue de contrôler la qualité des images produites en sortie des décodeurs numériques. Pour atteindre les objectifs visés dans cette étude, nous avons commencé par faire l'état de lieu de l'existant. L'examen critique des approches en usage a justifié la construction d'un ensemble de méthodes objectives d'évaluation de la qualité visuelle des images, basées sur des méthodes d'apprentissage automatique. Ces algorithmes prennent en entrées un ensemble de caractéristiques ou de métriques extraites des images. En fonction de ces caractéristiques, et de la disponibilité ou non d'une image de référence, deux sortes de mesures objectives ont été élaborées : la première basée sur des métriques avec référence, et la seconde basée sur des métriques sans référence ; toutes les deux à distorsions non spécifiques. En plus de ces méthodes d'évaluation objective, une méthode d'évaluation et d'amélioration de la qualité des images basée sur la détection et la correction des pixels défectueux dans les images a été mise en œuvre. Les applications ont contribué à affiner aussi bien les méthodes d'évaluation de la qualité visuelle des images que la construction des algorithmes objectifs de détection et de correction des pixels défectueux par rapport aux diverses méthodes actuellement en usage. Une implémentation sur cartes FPGA des techniques développées a été réalisée pour intégrer les modèles présentant les meilleures performances dans de la phase de simulation
Emerging 3D technologies for efficient implementation of FPGAs by Ogun Turkyilmaz( )

1 edition published in 2014 in English and held by 2 WorldCat member libraries worldwide

The ever increasing complexity of digital systems leads the reconfigurable architectures such as Field Programmable Gate Arrays (FPGA) to become highly demanded because of their in-field (re)programmability and low nonrecurring engineering (NRE) costs. Reconfigurability is achieved with high number of point configuration memories which results in extreme application flexibility and, at the same time, significant overheads in area, performance, and power compared to Application Specific Integrated Circuits (ASIC) for the same functionality. In this thesis, we propose to design FPGAs with several 3D technologies for efficient FPGA circuits. First, we integrate resistive memory based blocks to reduce the routing wirelength and widen FPGA employability for low-power applications with non-volatile property. Among many technologies, we focus on Oxide Resistive Memory (OxRRAM) and Conductive Bridge Resistive Memory (CBRAM) devices by assessing unique properties of these technologies in circuit design. As another solution, we design a new FPGA with 3D monolithic integration (3DMI) by utilizing high-density interconnects. Starting from two layers with logic-on-memory approach, we examine various partitioning schemes with increased number of integrated active layers to reduce the routing complexity and increase logic density. Based on the obtained results, we demonstrate that multi-tier 3DMI is a strong alternative for future scaling
Conception de SRAM ultra basse tension à haute efficacité énergétique basé sur de nouvelles technologies pour les applications IoT by Réda Boumchedda( )

1 edition published in 2019 in English and held by 2 WorldCat member libraries worldwide

The main constraint related to the IoT applications, is the low power consumption required withoutnecessarily compromising with the performance. Driven by the fast IoT market expansion, thearchitecture of the IoT nodes are evolving to best answer these constraints and propose the besttrade-off between the performance and the power consumption. The SRAM embedded in IoT nodecontributes greatly to the power consumption and is the bottleneck of performance. Therefore,optimizing their design is a priority. This thesis research work proposes different SRAM designs inthe context of an IoT node architecture using asynchronous logic to elevate the powerconsumption/performance trade-off.A single-rail TP SRAM is designed in 28nm FD-SOI technology specifically for asynchronous/asynchronous IoT node. This SRAM supports an asynchronous interfacecommunication and a fast transition sleep/active mode. This SRAM enables simultaneoussynchronous and asynchronous accesses on its two independent ports, as well as a selective virtualground (SVGND) to support ultra-low voltage in read operations. Measurements on a 64kbitsmemory macro prove the functionality for a supply voltage ranging from 0.25V to 1.25V. The sleepmode enables 158x reduction of the SVGND static-power consumption. The SVGND read assistachieves a gain of 50mV on the read port operations lowest voltage. The memory achieves, at 0.25Vand 27°C, an average energy cost per access of 1.45fJ/bit at 451kHz and a leakage of 25pW/bit insleep mode.To optimize the density of the SRAM, a 4T SRAM bitcell enhanced for both write and readoperations is proposed. The proposed bitcell is designed to respond to the requirements of energyconstrained systems, as in the case of most IoT-oriented circuits and applications. The use of 3DCoolCubeTM technology enables the design of a stable 4T SRAM bitcell by using data-dependentback bias (DDBB) and allows to enhance the density of SRAMs. The proposed bitcell architectureprovides a major reduction of the write operation energy consumption compared to a conventional6T bitcell. The SVGND assist ensures a full functionality at ultra-low voltage of read operations.Simulation results show reliable operations down to 0.35V close to six sigma (6ó) without any writeassist techniques (e.g. negative bitlines). The 4T bitcell achieves in worst case corner 300ns and125ns in write and read access time, respectively. A 6x energy consumption reduction compared toa low voltage/low leakge 6T bitcell is demonstrated.This thesis work resulted in several publications, a patent and a silicon implementation withvalidated results
Solutions alternatives pour améliorer le test de production des capteurs optiques en technologie CMOS by Richun Fei( )

1 edition published in 2015 in English and held by 2 WorldCat member libraries worldwide

Le test de production des imageurs CMOS est une étape clé du flot de fabrication afin de garantir des produits répondant aux critères de qualité et exempts de défauts de fabrication. Ces tests sont classifiés en test électrique et test optique. Le test électrique est basé sur du test structurel qui vérifie la partie numérique et certain blocks analogiques. La plus grande partie des circuits analogiques et la matrice des capteurs sont testés par le test optique. Ce test est basé sur des captures d'images et sur une recherche des défauts au moyen d'algorithmes de calcul spécifiques appliqué sur les images. Proche du fonctionnement applicatif, ils sont qualifies de test fonctionnels. La couverture des défauts obtenue par les tests de type fonctionnel est généralement inférieure à celle obtenue par un test structurel. L'objectif de cette thèse est d'étudier et développer des solutions de test alternatives aux tests fonctionnels afin d'obtenir des meilleurs taux de couverture de défauts, améliorant ainsi la fiabilité, tout en réduisant le temps de test et son coût. Parmi les défauts optiques qui ont causé des retours client par le passés, le défaut qui présent Horizontal Fixed Pattern Noise (HFPN) donnent lieu à un taux de couverture insuffisant. Ces recherches ont été orientées vers l'amélioration du taux de couverture de défauts dite de HFPN dans le test de production des imageurs CMOS.Le HFPN est défini comme une sorte d'image défaillante qui présente sous la forme des bandes résiduelles horizontales. Il est principalement causé par les défauts dans les lignes d'interconnexion qui alimentent et pilotent les pixels. La détection d'un défaut HFPN dans les tests optiques actuels est par comparer les valeurs moyennes de chaque ligne de pixels avec les lignes adjacentes. Si la différence d'une ligne par rapport aux lignes adjacentes est supérieur à la limites spécifié, la ligne est constaté comme défectueuse. Cette limite est donc difficile d'être ajusté face à un compromis entre le taux de couverture de ce défaut et le rendement.Dans cette thèse, nous avons proposé d'abord une amélioration de l'algorithme de détection pour améliorer le test optique actuelle. L'amélioration de test optique est validée par des résultats de test en production en appliquant le nouvel algorithme. Par la suite, une technique d'auto test (BIST) pour la détection des défauts dans les lignes d'interconnexion de matrice des pixels est étudiée et évalué. Enfin, une puce imageur avec le technique d'auto test embarqué est conçu et fabriqué pour la validation expérimentale
Conception et simulation des circuits numériques en 28nm FDSOI pour la haute fiabilité by Ajith Sivadasan( )

1 edition published in 2018 in English and held by 2 WorldCat member libraries worldwide

Scaling of classical CMOS technology provides an increase in performance of digital circuits owing to the possibility of incorporation of additional circuit components within the same silicon area. 28nm FDSOI technology from ST Microelectronics is an innovative scaling strategy maintaining a planar transistor structure and thus provide better performance with no increase in silicon chip fabrication costs for low power applications. It is important to ensure that the increased functionality and performance is not at the expense of decreased reliability, which can be ensured by meeting the requirements of international standards like ISO26262 for critical applications in the automotive and industrial settings. Semiconductor companies, to conform to these standards, are thus required to exhibit the capabilities for reliability estimation at the design conception stage most of which, currently, is done only after a digital circuit has been taped out. This work concentrates on Aging of standard cells and digital circuits with time under the influence of NBTI degradation mechanism for a wide range of Process, Voltage and Temperature (PVT) variations and aging compensation using backbiasing. One of the principal aims of this thesis is the establishment of a reliability analysis infrastructure consisting of software tools and gate level aging model in an industrial framework for failure rate estimation of digital circuits at the design conception stage for circuits developed using ST 28nm FDSOI technology
Etude de la variabilité des technologies PCM et OxRAM pour leur utilisation en tant que synapses dans les systèmes neuromorphiques by Daniele Garbin( )

1 edition published in 2015 in English and held by 2 WorldCat member libraries worldwide

The human brain is made of a large number of interconnected neural networks which are composed of neurons and synapses. With a low power consumption of only few Watts, the human brain is able to perform computational tasks that are out of reach for today's computers, which are based on the Von Neumann architecture. Neuromorphic hardware design, taking inspiration from the human brain, aims to implement the next generation, non-Von Neumann computing systems. In this thesis, emerging non-volatile memory devices, specifically Phase-Change Memory (PCM) and Oxide-based resistive memory (OxRAM) devices, are studied as artificial synapses in neuromorphic systems. The use of PCM devices as binary probabilistic synapses is studied for complex visual pattern extraction applications, evaluating the impact of the PCM programming conditions on the system-level power consumption.A programming strategy is proposed to mitigate the impact of PCM resistance drift. It is shown that, using scaled devices, it is possible to reduce the synaptic power consumption. The OxRAM resistance variability is evaluated experimentally through electrical characterization, gathering statistics on both single memory cells and at array level. A model that allows to reproduce OxRAM variability from low to high resistance state is developed. An OxRAM-based convolutional neural network architecture is then proposed on the basis of this experimental work. By implementing the computation of convolution directly in memory, the Von Neumann bottleneck is avoided. Robustness to OxRAM variability is demonstrated with complex visual pattern recognition tasks such as handwritten characters and traffic signs recognition
Architectural exploration methods and tools for heterogeneous 3D-IC by Felipe Frantz Ferreira( Book )

2 editions published in 2012 in French and held by 2 WorldCat member libraries worldwide

L'intégration tridimensionnelle (3D), où plusieurs puces sont empilées et interconnectées, est en train de révolutionner l'industrie des semi-conducteurs.Cette technologie permet d'associer, dans un même boîtier, des puces électroniques (analogique, numérique, mémoire) avec des puces d'autres domaines(MEMS, bio-capteurs, optique, etc). Cela ouvre de nombreuses voies d'innovation. Néanmoins, l'absence d'outils de conception assistée ordinateur(CAO) adaptés aux systèmes 3D freine l'adoption de la technologie.Cette thèse contribue à deux problématiques liées à la conception 3D : le partitionnement d'un système sur de multiples puces et l'optimisation hiérarchique de systèmes multiphysiques (hétérogènes).La première partie de la thèse est dédiée au problème de partitionner la fonctionnalité d'un système sur de multiples puces. Un outil de « floorplan » 3D a été développé pour optimiser ce partitionnement en fonction de la surface des puces, de la température d'opération du circuit et de la structure des interconnexions. Ce type d'outil étant complexe, nous proposons de régler ses paramètres de façon automatique par l'utilisation d'algorithmes évolutionnaires.Des résultats expérimentaux sur une suite de benchmarks et sur une architecture multi processeur connecté en réseau démontrent l'efficacité et l'applicabilité des techniques d'optimisation proposées.Dans la deuxième partie, nous présentons une méthodologie de conception hiérarchique qui est adaptée aux systèmes hétérogènes. La méthode combine une approche ascendante et descendante et utilise des courbes de compromis(Fronts de Pareto) comme une abstraction de la performance d'un circuit.La contribution principale de la thèse consiste à utiliser des techniques d'interpolation pour représenter les Fronts de Pareto par des fonctions continues et à leur intégration dans des processus d'optimisation classiques. Cela permet un gain en flexibilité lors de l'étape ascendante du flot (caractérisation) et un gain en temps lors de l'étape descendante (synthèse). Le flot de conception est démontré sur un amplificateur opérationnel ainsi comme sur la synthèse d'un lien optoélectronique avec trois niveaux hiérarchiques
Méthodes d'analyse de la variabilité et de conception robuste des circuits analogiques dans les technologies CMOS avancées by Hubert Filiol( Book )

2 editions published in 2010 in French and held by 2 WorldCat member libraries worldwide

With the continuous downscaling of CMOS technology, precise control over process parameters has become a highly challenging task. Due to the fluctuations in the manufacturing process, the performance of integrated circuits (ICs) will vary greatly between chips. Therefore, efficient methods to analyze such variability are essential to guarantee that fabricated ICs will meet the design and yield specifications. The classical methods for variability analysis are either pessimistic, thus leading to overdesign (worst-case analysis), or computing time expensive (Monte Carlo analysis). As for robust design methods, they are generally based on local optimization algorithms that locally improve the yield, but may not guarantee that the globally robust sizing is found. In this work, a new method for variability analysis and a new approach to design robust analog circuits are developed. The method dedicated to variability analysis consists of building polynomial models of the circuit performance metrics with the Design of Experiments theory, and then estimating the extreme variations by means of the Cornish-Fisher expansion. Compared to Monte Carlo analysis, this method shows a good accuracy without the shortcoming of a large computing cost. Finally, the robust design approach applies the previous variability analysis method in an intervalbasedoptimization algorithm to obtain a globally robust sizing
Statistical methodologies for modelling the impact of process variability in ultra-deep-submicron SRAMs by Kaya Can Akyel( )

1 edition published in 2014 in English and held by 2 WorldCat member libraries worldwide

The downscaling of device geometry towards its physical limits exacerbates the impact of the inevitable atomistic phenomena tied to matter granularity. In this context, many different variability sources raise and affect the electrical characteristics of the manufactured devices. The variability-aware design methodology has therefore become a popular research topic in the field of digital circuit design, since the increased number of transistors in the modern integrated circuits had led to a large statistical variability affecting dramatically circuit functionality. Static Random Access Memory (SRAM) circuits which are manufactured with the most aggressive design rules in a given technology node and contain billions of transistor, are severely impacted by the process variability which stands as the main obstacle for the further reduction of the bitcell area and of its minimum operating voltage. The reduction of the latter is a very important parameter for Low-Power design, which is one of the most popular research fields of our era. The optimization of SRAM bitcell design therefore has become a crucial task to guarantee the good functionality of the design at an industrial manufacturing level, in the same time answering to the high density and low power demands. However, the long time required by each new technology node process development means a long waiting time before obtaining silicon results, which is in cruel contrast with the fact that the design optimization has to be started as early as possible. An efficient SPICE characterization methodology for the minimum operating voltage of SRAM circuits is therefore a mandatory requirement for design optimization. This research work concentrates on the development of the new simulation methodologies for the modeling of the process variability in ultra-deep-submicron SRAMs, with the ultimate goal of a significantly accurate modeling of the minimum operating voltage Vmin. A particular interest is also carried on the time-dependent sub-class of the process variability, which appears as a change in the electrical characteristics of a given transistor during its operation and during its life-time. This research work has led to many publications and one patent application. The majority of findings are retained by STMicroelectronics SRAM development team for a further use in their design optimization flow
Conception et développement de circuits logiques de faible consommation et fiables basés sur des jonctions tunnel magnétiques à écriture par transfert de spin by Erya Deng( )

1 edition published in 2017 in English and held by 2 WorldCat member libraries worldwide

With the shrinking of CMOS (complementary metal oxide semi-conductor) technology, static and dynamic power increase dramatically and indeed has become one of the main challenges due to the increasing leakage current and long transfer distance between memory and logic chips. In the past decades, spintronics devices, such as spin transfer torque based magnetic tunnel junction (STT-MTJ), are widely investigated to overcome the static power issue thanks to their non-volatility. Hybrid logic-in-memory (LIM) architecture allows spintronics devices to be fabricated over the CMOS circuit plane, thereby reducing the transfer latency and the dynamic power dissipation. This thesis focuses on the design of hybrid MTJ/CMOS logic circuits and memories for low-power computing system.By using a compact MTJ model and the STMicroelectronics design kit for regular CMOS design, we investigate the hybrid MTJ/CMOS circuits for single-bit and multi-bit reading and writing. Optimization methods are also introduced to improve the reliability, which is extremely important for logic circuits where error correction blocks cannot be easily embedded without sacrificing their performances or adding extra area to the circuit. We extend the application of multi-context hybrid MTJ/CMOS structure to the memory design. Magnetic random access memory (MRAM) with simple peripheral circuits is designed.Based on the LIM concept, non-volatile logic/arithmetic circuits are designed to integrate MTJs not only as storage elements but also as logic operands. First, we design and theoretically analyze the non-volatile logic gates (NVLGs) including NOT, AND, OR and XOR. Then, 1-bit and 8-bit non-volatile full-adders (NVFAs), the basic elements for arithmetic operations, are proposed and compared with the traditional CMOS-based full-adder. The effect of CMOS transistor sizing and the MTJ parameters on the performances of NVFA is studied. Furthermore, we optimize the NVFA from two levels. From the structure-level, an ultra-high reliability voltage-mode sensing circuit is used to store the operand of NVFA. From the device-level, we propose 3-terminal MTJ switched by spin-Hall-assisted STT to replace the 2-terminal MTJ because of its smaller writing time and power consumption. Based on the NVLGs and NVFAs, other logic circuits can be built, for instance, non-volatile subtractor.Finally, non-volatile content addressable memory (NVCAM) is proposed. Two magnetic decoders aim at selecting a word line to be read or written and saving the corresponding search location in non-volatile state
Micro-capteurs de courant non-intrusifs autonomes sur support souple by Cyril Jacquemod( )

2 editions published in 2016 in French and held by 2 WorldCat member libraries worldwide

Part of the CIFRE contract in collaboration with Qualisteo company, this thesis focuses on the design and development of current sensors suitable for large voltage and current ranges for a tertiary or industrial or electrical installation. These new sensors allows to obtain control over the management of power consumption, featuring a network through the current measurement. These transmitted data will return the variations of the charging curve with sufficient detail to allow to recognize the equipment in operation, limiting at the same time the size of the information provided by several orders of magnitude compared to the original signal.The first part of this thesis presents the work done in order to develop innovative sensors. The developed sensors will proposed an answer to respond to the problems related to continuous and transient states. The solutions are based on the Rogowski technology which has the advantage of excellent linearity and measuring a wide dynamic with only one device. Coil sensitivity, linearity, time domain and FFT measurements are some of the mains parameters to judge the static characteristics of the Rogowski coil.The response of this new sensors have been increased as the design and technologies have been tested. Measurements on measuring benches made by the laboratory and field trials enabled to specify and design an electronic treatment, for the specific purpose of achieving a dedicated circuit.The second part of this work concerns the signal conditioning. The aim is to make the wireless sensor using Bluetooth Low Energy technology and use of an electronic system including RF transmitter implemented
Ambipolar independent double gate FET (Am -IDGFET) logic design : methods and techniques by Kotb Jabeur( Book )

2 editions published in 2012 in English and held by 2 WorldCat member libraries worldwide

The continuous growth of global demand for semiconductor products (in a broad range of sectors, such as security, healthcare, entertainment, connectivity, energy, etc.) has been both enabled and fuelled by Moore's law and regular doubling of circuit density and performance increases. However, as CMOS technology scaling begins to reach its theoretical limits, the ITRS predicts a new era known as “Beyond CMOS”. Novel materials and devices show an ability to complement or even replace the CMOS transistor or its channel in systems on chip with silicon-based technology. This has led to the identification of promising phenomena such as ambipolar conduction in quasi one- and zero-dimensional structures, for example in carbon nanotubes, graphene and silicon nanowires. Ambipolarity, in a dual-gate context (DG-FETs), means that n- and p-type behavior can be observed in the same device depending on the backgate voltage polarity. In addition to their attractive performances and the low power consumption, ambipolar double gate devices enable the development of completely new circuit structures and design paradigms. Conventional logic synthesis techniques cannot represent the capability of DG-FETs to operate as either n-type or p-type switches and new techniques must be found to build optimal logic. The work in this thesis explores design techniques to enable the use of such devices by defining generic approaches and design techniques based on ambipolar DG-FETs. Two different contexts are tackled: (i) improving standard cell logic design with more compact structures and better performance, as well as low-power design techniques exploiting the fourth terminal of the device, and (ii) adapting conventional logic synthesis and verification techniques such as Binary Decision Diagrams or Function Classification to ambipolar DGFETs in order to build reconfigurable logic cells. The proposed methods and techniques are validated and evaluated in a case study focused on DG-CNTFET through accurate simulations, using the most mature and recent DG-CNTFET model available in the literature
Développement d'architectures HW/SW tolérantes aux fautes et auto-calibrantes pour les technologies Intégrées 3D by Vladimir Pasca( )

1 edition published in 2013 in French and held by 2 WorldCat member libraries worldwide

3D technology promises energy-efficient heterogeneous integrated systems, which may open the way to thousands cores chips. Silicon dies containing processing elements are stacked and connected by vertical wires called Through-Silicon-Vias. In 3D chips, interconnecting an increasing number of processing elements requires a scalable high-performance interconnect solution: the 3D Network-on-Chip. Despite the advantages of 3D integration, testing, reliability and yield remain the major challenges for 3D NoC-based systems. In this thesis, the TSV interconnect test issue is addressed by an off-line Interconnect Built-In Self-Test (IBIST) strategy that detects both structural (i.e. opens, shorts) and parametric faults (i.e. delays and delay due to crosstalk). The IBIST circuitry implements a novel algorithm based on the aggressor-victim scenario and alleviates limitations of existing strategies. The proposed Kth-aggressor fault (KAF) model assumes that the aggressors of a victim TSV are neighboring wires within a distance given by the aggressor order K. Using this model, TSV interconnect tests of inter-die 3D NoC links may be performed for different aggressor order, reducing test times and circuitry complexity. In 3D NoCs, TSV permanent and transient faults can be mitigated at different abstraction levels. In this thesis, several error resilience schemes are proposed at data link and network levels. For transient faults, 3D NoC links can be protected using error correction codes (ECC) and retransmission schemes using error detection (Automatic Retransmission Query) and correction codes (i.e. Hybrid error correction and retransmission).For transients along a source-destination path, ECC codes can be implemented at network level (i.e. Network-level Forward Error Correction). Data link solutions also include TSV repair schemes for faults due to fabrication processes (i.e. TSV-Spare-and-Replace and Configurable Serial Links) and aging (i.e. Interconnect Built-In Self-Repair and Adaptive Serialization) defects. At network-level, the faulty inter-die links of 3D mesh NoCs are repaired by implementing a TSV fault-tolerant routing algorithm. Although single-level solutions can achieve the desired yield / reliability targets, error mitigation can be realized by a combination of approaches at several abstraction levels. To this end, multi-level error resilience strategies have been proposed. Experimental results show that there are cases where this multi-layer strategy pays-off both in terms of cost and performance. Unfortunately, one-fits-all solution does not exist, as each strategy has its advantages and limitations. For system designers, it is very difficult to assess early in the design stages the costs and the impact on performance of error resilience. Therefore, an error resilience exploration (ERX) methodology is proposed for 3D NoCs
Fast scalable and variability aware CMOS image sensor simulation methodology by Zhenfu Feng( Book )

2 editions published in 2014 in English and held by 2 WorldCat member libraries worldwide

The resolution of CMOS image sensor is becoming higher and higher, while for identifying its performance, designers need to do a series of simulations, and this work consumes large CPU time in classical design environment. This thesis titled "Fast Scalable and Variability Aware CMOS Image Sensor Simulation Methodology" is dedicated to explore a new simulation methodology for improving the simulation capability. This simulation methodology is used to study the image sensor performance versus low level design parameter, such as transistor size and process variability. The simulation methodology achieves error less than 0.4% on 3T-APS architecture. The methodology is tested in various pixel architectures, and it is used in simulating image sensor with 15 million pixels, the simulation capability is improved 64 times and time consumption is reduced from days to minutes. The potential application includes simulating array-based circuit, such as memory circuit matrix simulation
Impact du claquage progressif de l'oxyde sur le fonctionnement des composants et circuits élémentaires MOS : caractérisation et modélisation by Louis Gerrer( )

1 edition published in 2011 in French and held by 2 WorldCat member libraries worldwide

La progressivité du claquage des oxydes de grille d'épaisseurs inférieures à 20 nm permet d'envisager une prolongation de la durée de vie des circuits. Cet enjeu majeur de la fiabilité contemporaine requiert des modèles adaptés afin de contrôler la variabilité des paramètres induites par le claquage. Après avoir étudié l'impact d'une fuite de courant sur une couche chargée, nous avons mis au point un modèle bas niveau de simulation par éléments finis, capable de reproduire la dérive des paramètres mesurée sur des dispositifs du nœud 45 nm. Des lois empiriques de ces dérives ont été injectées dans un modèle compact du transistor dégradé, simplifié par nos observations originales de la dépolarisation du canal et de la répartition des courants. Finalement nous avons simulé l'impact du claquage sur le fonctionnement de circuits simples et estimés la dérive de leurs paramètres tels que l'augmentation de la consommation due au claquage
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Integrated optical interconnect architectures for embedded systems
Integrated optical interconnect architectures for embedded systems
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