WorldCat Identities

Pelcat, Maxime

Works: 20 works in 41 publications in 2 languages and 665 library holdings
Genres: Conference papers and proceedings 
Roles: Editor, Author, htt, Other, Contributor, Publishing director, Thesis advisor, Opponent, Programmer
Classifications: QA76.9.A73, 005.1
Publication Timeline
Most widely held works by Maxime Pelcat
Physical layer multi-core prototyping : a dataflow-based approach for LTE eNodeB by Maxime Pelcat( )

11 editions published between 2012 and 2013 in English and held by 371 WorldCat member libraries worldwide

Base stations developed according to the 3GPP Long Term Evolution (LTE) standard require unprecedented processing power. 3GPP LTE enables data rates beyond hundreds of Mbits/s by using advanced technologies, necessitating a highly complex LTE physical layer. The operating power of base stations is a significant cost for operators, and is currently optimized using state-of-the-art hardware solutions, such as heterogeneous distributed systems. The traditional system design method of porting algorithms to heterogeneous distributed systems based on test-and-refine methods is a manual, thus time-expensive, task. Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach for LTE eNodeB provides a clear introduction to the 3GPP LTE physical layer and to dataflow-based prototyping and programming. The difficulties in the process of 3GPP LTE physical layer porting are outlined, with particular focus on automatic partitioning and scheduling, load balancing and computation latency reduction, specifically in systems based on heterogeneous multi-core Digital Signal Processors. Multi-core prototyping methods based on algorithm dataflow modeling and architecture system-level modeling are assessed with the goal of automating and optimizing algorithm porting. With its analysis of physical layer processing and proposals of parallel programming methods, which include automatic partitioning and scheduling, Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach for LTE eNodeB is a key resource for researchers and students. This study of LTE algorithms which require dynamic or static assignment and dynamic or static scheduling, allows readers to reassess and expand their knowledge of this vital component of LTE base station design
Embedded Computer Systems: Architectures, Modeling, and Simulation : 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings by A Orailoglu( )

11 editions published in 2019 in English and held by 269 WorldCat member libraries worldwide

This book constitutes the refereed proceedings of the 19th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2019, held in Pythagorion, Samos, Greece, in July 2019. The 21 regular papers presented were carefully reviewed and selected from 55 submissions. The papers are organized in topical sections on system design space exploration; deep learning optimization; system security; multi/many-core scheduling; system energy and heat management; many-core communication; and electronic system-level design and verification. In addition there are 13 papers from three special sessions which were organized on topics of current interest: insights from negative results; machine learning implementations; and European projects
Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCs by Manel Ammar( )

1 edition published in 2017 in English and held by 2 WorldCat member libraries worldwide

Efficient DVFS for low power HEVC software decoder by Erwan Nogues( )

1 edition published in 2016 in English and held by 2 WorldCat member libraries worldwide

Probabilistic Approach Versus Machine Learning for One-Shot Quad-Tree Prediction in an Intra HEVC Encoder by Alexandre Mercat( )

1 edition published in 2018 in English and held by 2 WorldCat member libraries worldwide

Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs In-Depth Study of a Computer Vision Application by Karol Desnos( )

1 edition published in 2014 in English and held by 2 WorldCat member libraries worldwide

Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing Technologies by John McAllister( )

1 edition published in 2016 in English and held by 2 WorldCat member libraries worldwide

Low power HEVC software decoder for mobile devices by Erwan Raffin( )

1 edition published in 2015 in English and held by 2 WorldCat member libraries worldwide

On predicting the HEVC intra quad-tree partitioning with tunable energy and rate-distortion by Alexandre Mercat( )

1 edition published in 2018 in English and held by 2 WorldCat member libraries worldwide

An Open Framework for Rapid Prototyping of Signal Processing Applications by Maxime Pelcat( )

1 edition published in 2009 in English and held by 2 WorldCat member libraries worldwide

Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing by Zheng Zhou( )

1 edition published in 2014 in English and held by 2 WorldCat member libraries worldwide

Energy-Awareness and Performance Management with Parallel Dataflow Applications by Simon Holmbacka( )

1 edition published in 2015 in English and held by 2 WorldCat member libraries worldwide

Exploring the performances of partial reconfiguration in the context of image processing acceleration on FPGA-based smart cameras by El Mehdi Abdali( )

1 edition published in 2020 in English and held by 1 WorldCat member library worldwide

Les FPGAs sont des circuits d'accélération qui contiennent des ressources de calcul pouvant être librement interconnectées selon l'algorithme désiré. Cette flexibilité a rendu les FPGAs plus adaptés à implémenter efficacement des structures de calcul en flot de données où chaque noeud de calcul reçoit directement ses données à partir des noeuds qui les produisent. Ces structures sont plus efficaces quand la production et la consommation de données s'effectuent sans retard en ayant les noeuds simultanément exécutés. Toutefois, le nombre limité de ressources dans un FPGA ne permet pas une implémentation simultanée des différents noeuds. En effet, malgré leurs performances d'exécution élevées pour le flot de données, les FPGAs ne peuvent implémenter des gros algorithmes tels que des traitements d'images qui sont complexes.La Dynamic and Partial Reconfiguration (DPR) permet de reconfigurer une partie du circuit sans interrompre les autres parties exécutant d'autres tâches. Elle offre la possibilité de réutiliser les ressources et d'implémenter des algorithmes dépassant la capacité réelle du FPGA sur le détriment du temps global d'exécution. Néanmoins, la DPR s'accompagne de plusieurs paramètres de conception qui affecteront ses performances. Ces paramètres sont liés principalement la façon de partitionner et le FPGA en zones reconfigurables et l'application à implémenter en petites tâches avant de décider sur la stratégie d'ordonnecement de ces tâches ainsi que la communication entre les zones. Cette thèse étudie les possibilités et les défies d'utiliser la DPR pour rendre l'implémentation des algorithmes de vision par ordinateur sur FPGA plus efficient en matière de ressources. La thèse étudie également les capacités de cette technonolgie à améliorer les performances dans des implémentations autres que le calcul, tel que la communication
Conception d'une caméra intelligente multi-vues à base de FPGA by Jonathan Bonnard( )

1 edition published in 2021 in French and held by 1 WorldCat member library worldwide

Vision systems are an integral part of our society and continue to fuel many areas of research and development. Multi-view systems increase the field of vision applications by their ability to capture a scene from different view angles. Stereoscopic vision, 3D or panoramic-view systems are concrete examples of multi-view applications and are already massively used in both heavy and consumer industries. For example, some film productions use special effects from dozens of synchronized cameras. Observation satellites use camera arrays to create high-resolution images. This versatility, the diversity or redundancy of visual information can be exploited in many domains and in particular for artificial intelligence applied to vision.Recent researches have demonstrated that classical vision algorithms have become obsolete since the emergence of convolutional neural networks (CNNs). However, CNNs remain extremely expensive in terms of computation, therefore, complex to implement on low power electronics. In theory, reprogrammable circuits (FPGA) have a significant potential to infer a convolutional network as close as possible to an image sensor with a data stream oriented model of computation, guaranteeing both low power consumption and high-speed of execution. In practice, they remain limited by their low density of logic elements and other factors inherent to the technology. As a result, a single FPGA can only support a subset of a network. In this thesis, we propose a multi-view hardware architecture to increase the integration factor of a network on this type of hardware target. Indeed, even in its simplest form, a multi-view convolutional neural network architecture has a better recognition capacity than its single-view counterpart. This fundamental principle poses the question of the balance between the quantitative and qualitative factors of a network, i.e., the density of parameters defining the complexity of a CNN and its level of performance in terms of recognition. This work demonstrates experimentally that the multi-view nature of the information allows to decrease the quantity of parameters of a network and as a consequence, its complexity. An embedded camera prototype is proposed to test this hypothesis in a realistic context. It is divided into two parts.The first one is composed of several reprogrammable camera heads capable of inferring a part of a CNN by supporting the throughput of an image sensor. These are driven and powered by the second part composed of a central FPGA that aggregates the data stream from each sensor and executes the rest of the neural network. Among other things, this camera is able to synchronize or to add delays for each shot with a time baseof the order of ten nanoseconds
Prototypage Rapide et Génération de Code pour DSP Multi-Coeurs Appliqués à la Couche Physique des Stations de Base 3GPP LTE by Maxime Pelcat( Book )

2 editions published in 2010 in French and held by 1 WorldCat member library worldwide

The 3GPP Long Term Evolution (LTE) is a new terrestrial telecommunication standard which base stations, named eNodeB, necessitate much power to process the data transmitted and received by the LTE antennas. Digital Signal Processors (DSP) are commonly employed to compute physical layer algorithms in base stations. Modern DSPs are highly complex and heterogeneous systems. No ideal solution has been found to automatically assign application parts over the multiple cores contained in an eNodeB. In this thesis, we design a rapid prototyping and code generation framework that assists programmers of multi-core DSPs by automating the most complex design phases. As some algorithms of the LTE physical layer are too variable for static assignment, we present a simple adaptive scheduler that computes real-time assignment choices based on predicted execution times
ArKalon( )

1 edition published in 2013 in English and held by 1 WorldCat member library worldwide

Reconfigurable hardware acceleration of CNNs on FPGA-based smart cameras by Kamel Abdelouahab( )

1 edition published in 2018 in English and held by 1 WorldCat member library worldwide

Les Réseaux de Neurones Convolutifs profonds (CNNs) ont connu un large succès au cours de la dernière décennie, devenant un standard de la vision par ordinateur. Ce succès s'est fait au détriment d'un large coût de calcul, où le déploiement des CNNs reste une tâche ardue surtout sous des contraintes de temps réel.Afin de rendre ce déploiement possible, la littérature exploite le parallélisme important de ces algorithmes, ce qui nécessite l'utilisation de plate-formes matérielles dédiées. Dans les environnements soumis à des contraintes de consommations énergétiques, tels que les nœuds des caméras intelligentes, les cœurs de traitement à base de FPGAs sont reconnus comme des solutions de choix pour accélérer les applications de vision par ordinateur. Ceci est d'autant plus vrai pour les CNNs, où les traitements se font naturellement sur un flot de données, rendant les architectures matérielles à base de FPGA d'autant plus pertinentes. Dans ce contexte, cette thèse aborde les problématiques liées à l'implémentation des CNNs sur FPGAs. En particulier, ces travaux visent à améliorer l'efficacité des implantations grâce à deux principales stratégies d'optimisation; la première explore le modèle et les paramètres des CNNs, tandis que la seconde se concentre sur les architectures matérielles adaptées au FPGA
Energy optimization of Signal Processing on MPSoCs and its Application to Video Decoding by Erwan Nogues( )

1 edition published in 2016 in French and held by 0 WorldCat member libraries worldwide

Consumer electronics offer today more and more features (video, audio, GPS, Internet) and connectivity means (multi-radio systems with WiFi, Bluetooth, UMTS, HSPA, LTE-advanced ... ). The power demand of these devices is growing for the digital part especially for the processing chip. To support this ever increasing computing demand, processor architectures have evolved with multicore processors, graphics processors (GPU) and ether dedicated hardware accelerators. However, the evolution of battery technology is itself slower. Therefore, the autonomy of embedded systems is now under a great pressure. Among the new functionalities supported by mobile devices, video services take a prominent place. lndeed, recent analyzes show that they will represent 70% of mobile Internet traffic by 2016. Accompanying this growth, new technologies are emerging for new services and applications. Among them HEVC (High Efficiency Video Coding) can double the data compression while maintaining a subjective quality equivalent to its predecessor, the H.264 standard. ln a digital circuit, the total power consumption is made of static power and dynamic power. Most of modern hardware architectures implement means to control the power consumption of the system. Dynamic Voltage and Frequency Scaling (DVFS) mainly reduces the dynamic power of the circuit. This technique aims to adapt the power of the processor (and therefore its consumption) to the actual load needed by the application. To control the static power, Dynamic Power Management (DPM or sleep modes) aims to stop the voltage supplies associated with specific areas of the chip. ln this thesis, we first present a model of the energy consumed by the circuit integrating DPM and DVFS modes. This model is generalized to multi-core integrated circuits and to a rapid prototyping tool. Thus, the optimal operating point of a circuit, i.e. the operating frequency and the number of active cores, is identified. Secondly, the HEVC application is integrated to a multicore architecture coupled with a sophisticated DVFS mechanism. We show that this application can be implemented efficiently on general purpose processors (GPP) while minimizing the power consumption. Finally, and to get further energy gain, we propose a modified HEVC decoder that is capable to tune its energy gains together with a decoding quality trade-off
Runtime multicore scheduling techniques for dispatching parameterized signal and vision dataflow applications on heterogeneous MPSoCs by Julien Heulot( )

1 edition published in 2015 in English and held by 0 WorldCat member libraries worldwide

An important trend in embedded processing is the integration of increasingly more processing elements into Multiprocessor Systemson- Chip (MPSoC). This trend is due in part to limitations in processing power of individual elements that are caused by power consumption considerations. At the same time, signal processing applications are becoming increasingly dynamic in terms of their hardware resource requirements due to the growing sophistication of algorithms to reach higher levels of performance. In design and implementation of multicore signal processing systems, one of the main challenges is to dispatch computational tasks efficiently onto the available processing elements while taking into account dynamic changes in application functionality and resource requirements. An inefficient use can lead to longer processing times and higher energy consumption, making multicore task scheduling a very difficult problem to solve. Dataflow process network Models of Computation (MoCs) are widely used in design of signal processing systems. It decomposes application functionality into actors that communicate data exclusively through channels. The interconnection of actors and communication channels is modeled and manipulated as a directed graph, called a dataflow graph. There are different dataflow MoCs which offer different trade-off between predictability and expressiveness. These MoCs are widely used in design of signal processing systems due to their analyzability and their natural parallel expressivity. In this thesis, we propose a novel scheduling method to address multicore scheduling challenge. This scheduling method determines scheduling decisions strategically at runtime to optimize the overall execution time of applications onto heterogeneous multicore processing resources. Applications are described using the Parameterized and Interfaced Synchronous DataFlow (PiSDF) MoC. The PiSDF model allows describing parameterized application, making possible changes in application's resource requirement at runtime. At each execution, the parameterized dataflow is then transformed into a locally static one used to efficiently schedule the application with an a priori knowledge of its behavior. The proposed scheduling method have been tested and benchmarked on multiple state-of-the-art applications from computer vision, signal processing and multimedia domains
Memory Study and Dataflow Representations for Rapid Prototyping of Signal Processing Applications on MPSoCs by Karol Desnos( )

1 edition published in 2014 in English and held by 0 WorldCat member libraries worldwide

The development of embedded Digital Signal Processing (DSP) applications for Multiprocessor Systems-on-Chips (MPSoCs) is a complex task requiring the consideration of many constraints including real-time requirements, power consumption restrictions, and limited hardware resources. To satisfy these constraints, it is critical to understand the general characteristics of a given application: its behavior and its requirements in terms of MPSoC resources. In particular, the memory requirements of an application strongly impact the quality and performance of an embedded system, as the silicon area occupied by the memory can be as large as 80% of a chip and may be responsible for a major part of its power consumption. Despite the large overhead, limited memory resources remain an important constraint that considerably increases the development time of embedded systems. Dataflow Models of Computation (MoCs) are widely used for the specification, analysis, and optimization of DSP applications. The popularity of dataflow MoCs is due to their great analyzability and their natural expressivity of the parallelism of a DSP application. The abstraction of time in dataflow MoCs is particularly suitable for exploiting the parallelism offered by heterogeneous MPSoCs. In this thesis, we propose a complete method to study the important aspect of memory characteristic of a DSP application modeled with a dataflow graph. The proposed method spans the theoretical, architecture-independent memory characterization to the quasi-optimal static memory allocation of an application on a real shared-memory MPSoC. The proposed method, implemented as part of a rapid prototyping framework, is extensively tested on a set of state-of-the-art applications from the computer-vision, the telecommunication, and the multimedia domains. Then, because the dataflow MoC used in our method is unable to model applications with a dynamic behavior, we introduce a new dataflow meta-model to address the important challenge of managing dynamics in DSP-oriented representations. The new reconfigurable and composable dataflow meta-model strengthens the predictability, the conciseness and the readability of application descriptions
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Physical layer multi-core prototyping : a dataflow-based approach for LTE eNodeB
Embedded Computer Systems: Architectures, Modeling, and Simulation : 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings
English (37)

French (4)