Yajima, S.
Overview
Works:  32 works in 53 publications in 3 languages and 157 library holdings 

Roles:  Author, Inventor 
Publication Timeline
.
Most widely held works by
S Yajima
Concept of the semihomogeneous reactor (SHR) and present status of research in Japan by
S Yajima(
Book
)
9 editions published in 1961 in English and German and held by 66 WorldCat member libraries worldwide
9 editions published in 1961 in English and German and held by 66 WorldCat member libraries worldwide
Semihomogeneous hightemperature gascooled breeder reactors by K Inoue(
Book
)
in English and held by 32 WorldCat member libraries worldwide
in English and held by 32 WorldCat member libraries worldwide
On the expressive power of OBDDs with parametric variables and bounded cutwidth circuits by
Kazuyoshi Takagi(
Book
)
2 editions published in 1995 in English and held by 3 WorldCat member libraries worldwide
Abstract: "Ordered Binary Decision Diagrams (OBDDs) are widely used to represent Boolean functions. In this paper, we define VOBDDs by introducing existentially quantified parametric variables into OBDDs. Several methods which manipulate huge OBDDs in decomposed form can be regarded as methods based on VOBDDs. A theoretical bound of the expressive power of VOBDDs is shown. We introduce the notion of cutwidth of circuits and evaluate the computational power of bounded cutwidth circuits. This results [sic] suggests that the cutwidth and linear arrangement of circuits are closely related to the size and variable ordering of VOBDDs which represent the functions the circuits compute."
2 editions published in 1995 in English and held by 3 WorldCat member libraries worldwide
Abstract: "Ordered Binary Decision Diagrams (OBDDs) are widely used to represent Boolean functions. In this paper, we define VOBDDs by introducing existentially quantified parametric variables into OBDDs. Several methods which manipulate huge OBDDs in decomposed form can be regarded as methods based on VOBDDs. A theoretical bound of the expressive power of VOBDDs is shown. We introduce the notion of cutwidth of circuits and evaluate the computational power of bounded cutwidth circuits. This results [sic] suggests that the cutwidth and linear arrangement of circuits are closely related to the size and variable ordering of VOBDDs which represent the functions the circuits compute."
Regular constantdepth circuits characterized by pseudodefinite automata by
Shuzo Yajima(
Book
)
2 editions published in 1992 in English and held by 3 WorldCat member libraries worldwide
Abstract: "Problems computable sequentially by finite automata are known to be computable in parallel by logarithmicdepth combinational circuits. Typically a binary addition by a serial binary adder is also performed in parallel by a carrylookahead adder or a logarithmicdepth circuit. In this paper much faster computation or in a sense ultimate speed computation is discussed. A class of problems computable by constantdepth combinational circuits is characterized by automata. In particular the paper shows 'a problem computable by a regular constant depth circuit in parallel is computable sequentially by a newly introduced pseudodefinite automaton and vice versa.' Definite, quasidefinite and pseudodefinite automata are introduced. A typical example is a redundant binary addition. A serial redundant binary adder is a definite automaton, and its timeexpansion creates a parallel redundant binary adder, or a constantdepth circuit, which performs a carrypropagationfree addition."
2 editions published in 1992 in English and held by 3 WorldCat member libraries worldwide
Abstract: "Problems computable sequentially by finite automata are known to be computable in parallel by logarithmicdepth combinational circuits. Typically a binary addition by a serial binary adder is also performed in parallel by a carrylookahead adder or a logarithmicdepth circuit. In this paper much faster computation or in a sense ultimate speed computation is discussed. A class of problems computable by constantdepth combinational circuits is characterized by automata. In particular the paper shows 'a problem computable by a regular constant depth circuit in parallel is computable sequentially by a newly introduced pseudodefinite automaton and vice versa.' Definite, quasidefinite and pseudodefinite automata are introduced. A typical example is a redundant binary addition. A serial redundant binary adder is a definite automaton, and its timeexpansion creates a parallel redundant binary adder, or a constantdepth circuit, which performs a carrypropagationfree addition."
The complexity of the optimal variable ordering problems of shared binary decision diagrams by Seiichiro Tani(
Book
)
2 editions published in 1993 in English and held by 3 WorldCat member libraries worldwide
Abstract: "A binary decision diagram (BDD) proposed by Akers and Bryant is a directed acyclic graph for representing a Boolean function. BDD's are widely used in various areas which require Boolean function manipulation, since BDD's can represent efficiently many of Boolean functions for practical use and can have other desirable properties. A shared binary decision diagram (SBDD) is the extension of BDD's and represents more than one Boolean functions [sic]. Recently some improvements such as the introduction of attributed edges were proposed and SBDD's are used in wide areas such as logic design verification, test generation and logic synthesis. It is important to represent Boolean functions by the smaller size of BDD's or SBDD's, because computation time and storage requirements for Boolean function manipulation are highly influenced by the size of the graph. In general the number of nodes largely depends on the variable ordering. Therefore it is important to find a variable ordering that minimizes the size of the graph. From the theoretical point of view, it was shown by Bryant that the problem of computing a variable ordering that minimizes the size of the graph for a given Boolean formula is co NPcomplete. However it has not been shown how hard it is to solve the problem of finding an optimal variable ordering for a given BDD. There is the case that the number of nodes of BDD's (an SBDD) corresponding to the Boolean formulas of the polynomial size is exponential for any variable ordering (for example, multiplier functions). Thus, since it is impossible to show a trivial polynomial transformation from the problem for a given Boolean formula to the problem for a given BDD, the two problems are essentially different. In this report, it is proved that the optimal variable ordering problem of SBDD (OVO) is NP complete. The problem is to decide whether, for a given SBDD with n nodes and a positive integer k(<n), there exists a variable ordering for some graph whose nodes are less than or equal to k and which represents the same Boolean functions as are represented by the given SBDD."
2 editions published in 1993 in English and held by 3 WorldCat member libraries worldwide
Abstract: "A binary decision diagram (BDD) proposed by Akers and Bryant is a directed acyclic graph for representing a Boolean function. BDD's are widely used in various areas which require Boolean function manipulation, since BDD's can represent efficiently many of Boolean functions for practical use and can have other desirable properties. A shared binary decision diagram (SBDD) is the extension of BDD's and represents more than one Boolean functions [sic]. Recently some improvements such as the introduction of attributed edges were proposed and SBDD's are used in wide areas such as logic design verification, test generation and logic synthesis. It is important to represent Boolean functions by the smaller size of BDD's or SBDD's, because computation time and storage requirements for Boolean function manipulation are highly influenced by the size of the graph. In general the number of nodes largely depends on the variable ordering. Therefore it is important to find a variable ordering that minimizes the size of the graph. From the theoretical point of view, it was shown by Bryant that the problem of computing a variable ordering that minimizes the size of the graph for a given Boolean formula is co NPcomplete. However it has not been shown how hard it is to solve the problem of finding an optimal variable ordering for a given BDD. There is the case that the number of nodes of BDD's (an SBDD) corresponding to the Boolean formulas of the polynomial size is exponential for any variable ordering (for example, multiplier functions). Thus, since it is impossible to show a trivial polynomial transformation from the problem for a given Boolean formula to the problem for a given BDD, the two problems are essentially different. In this report, it is proved that the optimal variable ordering problem of SBDD (OVO) is NP complete. The problem is to decide whether, for a given SBDD with n nodes and a positive integer k(<n), there exists a variable ordering for some graph whose nodes are less than or equal to k and which represents the same Boolean functions as are represented by the given SBDD."
Minimum single transition time assignments using SBDD by YongJin Kwon(
Book
)
2 editions published in 1993 in English and held by 3 WorldCat member libraries worldwide
Abstract: "We propose a new method of the single transitiontime (STT) assignments for asynchronous sequential circuits, in which the propositional calculus, or Boolean algebra is adopted. Exact minimum solutions of the STT assignments are obtained by our method. In order to handle huge propositional formulas, the shared binary decision diagrams (SBDD's) are used as an internal representation of the formulas which denote the STT assignment for a given normal flow table. Morever, as an application of the minimum algorithm, a minimum algorithm for the constrained encoding problems are [sic] also proposed, for which so far only heuristic algorithms are known for solving large and practical problems. However, our method always guarantees minimum solutions to be obtained. Experimental results show that our methods are effective to obtain minimum solutions at significantly reduced computation cost."
2 editions published in 1993 in English and held by 3 WorldCat member libraries worldwide
Abstract: "We propose a new method of the single transitiontime (STT) assignments for asynchronous sequential circuits, in which the propositional calculus, or Boolean algebra is adopted. Exact minimum solutions of the STT assignments are obtained by our method. In order to handle huge propositional formulas, the shared binary decision diagrams (SBDD's) are used as an internal representation of the formulas which denote the STT assignment for a given normal flow table. Morever, as an application of the minimum algorithm, a minimum algorithm for the constrained encoding problems are [sic] also proposed, for which so far only heuristic algorithms are known for solving large and practical problems. However, our method always guarantees minimum solutions to be obtained. Experimental results show that our methods are effective to obtain minimum solutions at significantly reduced computation cost."
Contribution to the calculation of intermediate diaphragms in box girders by
Masaharu Hirashima(
Book
)
2 editions published in 1979 in English and held by 3 WorldCat member libraries worldwide
2 editions published in 1979 in English and held by 3 WorldCat member libraries worldwide
Efficient construction of binary moment diagrams for verifying arithmetic circuits by
Kiyoharu Hamaguchi(
Book
)
2 editions published in 1995 in English and held by 3 WorldCat member libraries worldwide
Abstract: "Binary Decision Diagrams (BDDs) have been used as a very powerful tool for manipulating Boolean functions in various application domains, in particular, design verification of logic circuits. We can represent many practical functions with reasonable size of BDDs, and perform Boolean operations very efficiently. Unfortunately, the sizes of the BDDs for representing multiplication are known to blow up exponentially to the number of inputs. Binary Moment Diagrams (BMDs) are graph representations of mappings from binary vectors to integers. BMDs also provide canonical representations to those functions. When we use BMDs, we can represent the output function at the word level. We can represent the functions expressing multiplication with BMDs whose size grows only linearly with the number of variables. Bryant and Chen reported a BMDbased polynomialtime algorithm for verifying multipliers. This approach requires highlevel information such as specifications to subcomponents. From users' point of view, is is convenient to handle circuit descriptions without giving specifications to subcomponents. This paper presents a new technique called backward sweeping. Using this technique, we can verify arithmetic circuits without any highlevel information. Although our experiments are preliminary, the results for array multipliers and Wallacetree multipliers both show that the order of the computation time is approximately n[superscript 3.5], where n is the number of inputs. We have successfully verified 31bit Wallacetree multipliers in 260 seconds with 3 Mbyte of memory on SPARCstation 10/51. We have also built the *BMD for c6288 in 72 seconds with 2 Mbyte of memory. This result outperforms previous BDDbased approaches for verifying multipliers."
2 editions published in 1995 in English and held by 3 WorldCat member libraries worldwide
Abstract: "Binary Decision Diagrams (BDDs) have been used as a very powerful tool for manipulating Boolean functions in various application domains, in particular, design verification of logic circuits. We can represent many practical functions with reasonable size of BDDs, and perform Boolean operations very efficiently. Unfortunately, the sizes of the BDDs for representing multiplication are known to blow up exponentially to the number of inputs. Binary Moment Diagrams (BMDs) are graph representations of mappings from binary vectors to integers. BMDs also provide canonical representations to those functions. When we use BMDs, we can represent the output function at the word level. We can represent the functions expressing multiplication with BMDs whose size grows only linearly with the number of variables. Bryant and Chen reported a BMDbased polynomialtime algorithm for verifying multipliers. This approach requires highlevel information such as specifications to subcomponents. From users' point of view, is is convenient to handle circuit descriptions without giving specifications to subcomponents. This paper presents a new technique called backward sweeping. Using this technique, we can verify arithmetic circuits without any highlevel information. Although our experiments are preliminary, the results for array multipliers and Wallacetree multipliers both show that the order of the computation time is approximately n[superscript 3.5], where n is the number of inputs. We have successfully verified 31bit Wallacetree multipliers in 260 seconds with 3 Mbyte of memory on SPARCstation 10/51. We have also built the *BMD for c6288 in 72 seconds with 2 Mbyte of memory. This result outperforms previous BDDbased approaches for verifying multipliers."
Efficient initial approximation and fast converging algorithms for division and square root by
M Ito(
Book
)
2 editions published in 1995 in English and held by 3 WorldCat member libraries worldwide
Abstract: "With the increasing availability of highspeed multiplication units, convergencetype algorithms have become advantageous to the fast calculation of division and square root. Efficient initial approximation methods and fast converging algorithms are important to achieve the desired precision with a small number of operations and with small lookup tables. In this paper, a new initial approximation method for division, and accelerated higher order converging division algorithm, and a new square rooting algorithm are proposed. They are suitable for implementation on an arithmetic unit where one multiplyaccumulate operation can be executed in one cycle. In the case of double precision division, the combination of our initial approximation method and our converging algorithm requires only 1/5 to 1/50 the size of lookup tables as the NewtonRaphson based method. Our new square rooting algorithm can form a double precision square root faster using smaller lookup tables than the NewtonRaphson method."
2 editions published in 1995 in English and held by 3 WorldCat member libraries worldwide
Abstract: "With the increasing availability of highspeed multiplication units, convergencetype algorithms have become advantageous to the fast calculation of division and square root. Efficient initial approximation methods and fast converging algorithms are important to achieve the desired precision with a small number of operations and with small lookup tables. In this paper, a new initial approximation method for division, and accelerated higher order converging division algorithm, and a new square rooting algorithm are proposed. They are suitable for implementation on an arithmetic unit where one multiplyaccumulate operation can be executed in one cycle. In the case of double precision division, the combination of our initial approximation method and our converging algorithm requires only 1/5 to 1/50 the size of lookup tables as the NewtonRaphson based method. Our new square rooting algorithm can form a double precision square root faster using smaller lookup tables than the NewtonRaphson method."
Linear arrangement algorithms for VLSI layout of highspeed multipliers by
Kazuyoshi Takagi(
Book
)
2 editions published in 1993 in English and held by 3 WorldCat member libraries worldwide
Abstract: "Two algorithms for minimum cut linear arrangement of a class of graphs called pq dags are proposed. They are useful for VLSI layout design of the adder tree part of highspeed parallel multipliers such as Wallace tree. A pq dag is introduced for representing the connection scheme of an adder tree, and the VLSI layout problem of the adder tree part of a multiplier is treated as the minimum cut linear arrangement problem of its corresponding pq dag. One of the two algorithms is based on dynamic programming. It calculates an exact minimum solution within n[superscript O(1)] time and space, where n is the size of a given graph. The other algorithm is an approximation algorithm which calculates a solution with O(log n) cutwidth. It requires O(n log n) time."
2 editions published in 1993 in English and held by 3 WorldCat member libraries worldwide
Abstract: "Two algorithms for minimum cut linear arrangement of a class of graphs called pq dags are proposed. They are useful for VLSI layout design of the adder tree part of highspeed parallel multipliers such as Wallace tree. A pq dag is introduced for representing the connection scheme of an adder tree, and the VLSI layout problem of the adder tree part of a multiplier is treated as the minimum cut linear arrangement problem of its corresponding pq dag. One of the two algorithms is based on dynamic programming. It calculates an exact minimum solution within n[superscript O(1)] time and space, where n is the size of a given graph. The other algorithm is an approximation algorithm which calculates a solution with O(log n) cutwidth. It requires O(n log n) time."
Efficient hardware initial approximation method for multiplicative division and square root by
Masayuki Ito(
Book
)
2 editions published in 1995 in English and held by 3 WorldCat member libraries worldwide
Abstract: "An efficient initial approximation method for multiplicative division and square root is proposed. It is a modification of the linear approximation. The multiplication and the addition required for the linear approximation are replaced by only one multiplication with a slight modification of the operand. The modification of the operand can be performed by a simple circuit which is also used for implementing converging algorithms, such as NewtonRaphson's. The same accuracy is achieved as the linear approximation. In comparison with an approximation directly through table lookup, about twice many [sic] correct bits can be produced, and therefore, the first iteration of a converging algorithm which requires two or three multiplications can be removed. The proposed method makes it possible to achieve doubleprecision division and square root by only one iteration of converging algorithms. It directly produces singleprecision reciprocals and square roots."
2 editions published in 1995 in English and held by 3 WorldCat member libraries worldwide
Abstract: "An efficient initial approximation method for multiplicative division and square root is proposed. It is a modification of the linear approximation. The multiplication and the addition required for the linear approximation are replaced by only one multiplication with a slight modification of the operand. The modification of the operand can be performed by a simple circuit which is also used for implementing converging algorithms, such as NewtonRaphson's. The same accuracy is achieved as the linear approximation. In comparison with an approximation directly through table lookup, about twice many [sic] correct bits can be produced, and therefore, the first iteration of a converging algorithm which requires two or three multiplications can be removed. The proposed method makes it possible to achieve doubleprecision division and square root by only one iteration of converging algorithms. It directly produces singleprecision reciprocals and square roots."
Computational power of cubeconnected associative processor arrays under restrictions on communication by
Kazuyoshi Hayase(
Book
)
2 editions published in 1994 in English and held by 3 WorldCat member libraries worldwide
Abstract: "In this paper, we study the computational power of an SIMD type parallel computation model with simple processors, called cube APA. The cubeAPA consists of an associative processor array and a RAM. The RAM can control multiple processors in parallel according to the partial match with their indices. And each pair of processors can execute AND, OR logic operations on their data bits in parallel. Some relationships between the computational power of cubeAPAs that run with at most k alternations of logic operations in communication and the polynomial time hierarchy are stated."
2 editions published in 1994 in English and held by 3 WorldCat member libraries worldwide
Abstract: "In this paper, we study the computational power of an SIMD type parallel computation model with simple processors, called cube APA. The cubeAPA consists of an associative processor array and a RAM. The RAM can control multiple processors in parallel according to the partial match with their indices. And each pair of processors can execute AND, OR logic operations on their data bits in parallel. Some relationships between the computational power of cubeAPAs that run with at most k alternations of logic operations in communication and the polynomial time hierarchy are stated."
Size of ordered binary decision diagrams representing threshold functions by K Hosaka(
Book
)
2 editions published in 1994 in English and held by 3 WorldCat member libraries worldwide
Abstract: "An ordered binary decision diagram (OBDD) is a graph representation of a Boolean function. It is observed that OBDD's can represent many practical Boolean functions in feasible size. In this paper, the size of OBDD's representing threshold functions is studied. Two cases are treated: an ordering of variables is given in one case, and is selected to minimize the size of the OBDD in the other case. We prove that upper bounds for both cases are O(2[superscript n/2]), where n is the number of variables of threshold functions. We prove a lower bound of [omega](2[superscript n/2]) in the former case, and that of [omega](n2[superscript square root of n/2]) in the latter case."
2 editions published in 1994 in English and held by 3 WorldCat member libraries worldwide
Abstract: "An ordered binary decision diagram (OBDD) is a graph representation of a Boolean function. It is observed that OBDD's can represent many practical Boolean functions in feasible size. In this paper, the size of OBDD's representing threshold functions is studied. Two cases are treated: an ordering of variables is given in one case, and is selected to minimize the size of the OBDD in the other case. We prove that upper bounds for both cases are O(2[superscript n/2]), where n is the number of variables of threshold functions. We prove a lower bound of [omega](2[superscript n/2]) in the former case, and that of [omega](n2[superscript square root of n/2]) in the latter case."
Expressive power of readktimesonly branching programs by Y Takenaga(
Book
)
2 editions published in 1995 in English and held by 3 WorldCat member libraries worldwide
Abstract: "Expressive power of branching programs under restrictions on the number of times to read each input is considered. A blockwise branching program, on which input variables can be read several times in different orders, is defined and is compared with the models with different restrictions on the order to read inputs. It is proved that under readktimesonly restriction (k [> or =] 2), the expressive power of polynomial size oblivious branching programs, blockwise branching programs and (k, *)programs are different."
2 editions published in 1995 in English and held by 3 WorldCat member libraries worldwide
Abstract: "Expressive power of branching programs under restrictions on the number of times to read each input is considered. A blockwise branching program, on which input variables can be read several times in different orders, is defined and is compared with the models with different restrictions on the order to read inputs. It is proved that under readktimesonly restriction (k [> or =] 2), the expressive power of polynomial size oblivious branching programs, blockwise branching programs and (k, *)programs are different."
Dutch books on science and technology brought to Japan in 18th and 19th centuries by
S Yajima(
)
1 edition published in 1953 in English and held by 2 WorldCat member libraries worldwide
1 edition published in 1953 in English and held by 2 WorldCat member libraries worldwide
Les sciences physiques au Japon durant l'ere de Meiji (18681912) by
S Yajima(
)
1 edition published in 1956 in French and held by 2 WorldCat member libraries worldwide
1 edition published in 1956 in French and held by 2 WorldCat member libraries worldwide
Fracture properties of Xphase precipitation hardened ferritic stainless steel and ductility improvement of the steel by
Katsuaki Suganuma(
)
1 edition published in 1981 in English and held by 2 WorldCat member libraries worldwide
1 edition published in 1981 in English and held by 2 WorldCat member libraries worldwide
History of sciences in Japan by
S Yajima(
)
1 edition published in 1951 in English and held by 2 WorldCat member libraries worldwide
1 edition published in 1951 in English and held by 2 WorldCat member libraries worldwide
Thermal expansion of siliconated pyrolytic carbon by
Kosuke Aoki(
)
1 edition published in 1974 in English and held by 2 WorldCat member libraries worldwide
1 edition published in 1974 in English and held by 2 WorldCat member libraries worldwide
Identification and properties of ultrafine iron particles dispersed in a glasslike carbon matrix by M Omori(
)
1 edition published in 1979 in English and held by 2 WorldCat member libraries worldwide
1 edition published in 1979 in English and held by 2 WorldCat member libraries worldwide
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Algebra, Boolean Algorithms Approximation theory Asynchronous circuits Binary system (Mathematics) Boundary value problems Box beams Branching processes Combinatorial analysis Computational complexity Computer arithmetic Convergence Data structures (Computer science) Decision logic tables Directed graphs Dynamic programming Gas cooled reactors Integrated circuitsVery large scale integrationDesign and construction Logic circuits Logic design Logic designData processing Machine theory Multipliers (Mathematical analysis) NewtonRaphson method NPcomplete problems Nuclear physics Nuclear reactors Ordered algebraic structures Parallel processing (Electronic computers) Threshold logic Turing machines