WorldCat Identities

Portal, Jean-Michel (19..-....).

Overview
Works: 34 works in 35 publications in 2 languages and 49 library holdings
Roles: Other, Opponent, Thesis advisor, Author
Publication Timeline
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Most widely held works by Jean-Michel Portal
Caractérisation et modélisation de la variabilité au niveau du dispositif dans les MOSFET FD-SOI avancés by Krishna Pradeep( )

1 edition published in 2019 in French and held by 2 WorldCat member libraries worldwide

Selon l'esprit de la “loi de Moore” utilisant des techniques innovantes telles que l'intégration 3D et de nouvelles architectures d'appareils, le marché a également évolué pour commencer à imposer des exigences spécifiques aux composants, comme des appareils à faible consommation et à faible fuite, requis par l'Internet des objets (IoT) applications et périphériques hautes performances demandés par les applications 5-G et les centres de données. Ainsi, le secteur des semi-conducteurs s'est peu à peu laissé guider par les avancées technologiques, mais aussi par les applications.La réduction de la tension d'alimentation est encore plus importante pour les applications à faible puissance, comme dans l'IoT, cela est limité par la variabilité du périphérique. L'abaissement de la tension d'alimentation implique une marge réduite pour que les concepteurs gèrent la variabilité du dispositif. Cela nécessite un accès à des outils améliorés permettant aux concepteurs de prévoir la variabilité des périphériques et d'évaluer son effet sur les performances des leur conception, ainsi que des innovations technologiques permettant de réduire la variabilité des périphériques.Cette thèse se concentre dans la première partie et examine comment la variabilité du dispositif peut être modélisée avec précision et comment sa prévision peut être incluse dans les modèles compacts utilisés par les concepteurs dans leurs simulations SPICE. La thèse analyse d'abord la variabilité du dispositif dans les transistors FD-SOI avancés à l'aide de mesures directes. À l'échelle spatiale, en fonction de la distance entre les deux dispositifs considérés, la variabilité peut être classée en unités de fabrication intra-matrice, inter-matrice, inter-tranche, inter-lot ou même entre différentes usines de fabrication. Par souci de simplicité, toute la variabilité d'une même matrice peut être regroupée en tant que variabilité locale, tandis que d'autres en tant que variabilité globale. Enfin, entre deux dispositifs arbitraires, il y aura des contributions de la variabilité locale et globale, auquel cas il est plus facile de l'appeler la variabilité totale. Des stratégies de mesure dédiées sont développées à l'aide de structures de test spécialisées pour évaluer directement la variabilité à différentes échelles spatiales à l'aide de caractérisations C-V et I-V. L'effet de la variabilité est d'abord analysé sur des facteurs de qualité (FOM) sélectionnés et des paramètres de procédés extraits des courbes C-V et I-V, pour lesquels des méthodologies d'extraction de paramètres sont développées ou des méthodes existantes améliorées. Cette analyse aide à identifier la distribution des paramétres et les corrélations possibles présentes entre les paramètres.Ensuite, nous analysons la variabilité dépendante de la polarisation dans les courbes I-V et C-V. Pour cela, une métrique universelle, qui fonctionne quelle que soit l'échelle spatiale de la variabilité, est definée sur la base de l'analyse des appariement précédemment rapportée pour la variabilité locale. Cette thèse étend également cette approche à la variabilité globale et totale. L'analyse de l'ensemble des courbes permet de ne pas manquer certaines informations critiques dans une plage de polarisation particulière, qui n'apparaissaient pas dans les FOM sélectionnés.Une approche de modélisation satistique est utilisée pour modéliser la variabilité observée et identifier les sources de variations, en termes de sensibilité à chaque source de variabilité, en utilisant un modèle physique compact comme Leti-UTSOI. Le modèle compact est d'abord étalonné sur les courbes C-V et I-V dans différentes conditions de polarisation et géométries. L'analyse des FOM et de leurs corrélations a permis d'identifier les dépendances manquantes dans le modèle compact. Celles-ci ont également été incluses en apportant de petites modifications au modèle compact
Optimisation des mémoires résistives OxRAM à base d'oxydes métalliques pour intégration comme mémoires embarquées dans un nœud technologique CMOS avancé by Mourad Azzaz( )

1 edition published in 2017 in French and held by 2 WorldCat member libraries worldwide

Embedded Flash memories integration on advanced CMOS technological nodes such as the 28nm leads to serious compatibility problems with the new manufacturing steps such as the high-permittivity gate dielectric, the use of metal gate, etc. The addition of a conventional double-grid device such as the one for Flash appears to be very expensive in terms of number of masks and additional manufacturing steps. Many alternatives have emerged: phase change memories PCRAM, magnetic memories MRAM and resistive memories OxRAM. However, the high programming current of the PCRAM memories and the risks associated to the contamination of the materials used for the MRAM memories represent the weak points of these technologies. On the other hand, OxRAM memories are particularly attractive for integration as CMOS embedded memory. The materials used (metal oxide dielectric such as HfO₂ or Ta₂O₅) compatible with the CMOS manufacturing process and their low programming voltages due to filament conduction are an advantage for OxRAM memories.In this thesis, an in depth memory stack optimization is done to make up the OxRAM memory cell in order to be integrated into a matrix of memories. Thus, various top and bottom electrodes and various switching oxides have been studied in order to better control and improve the variability of the resistive states of the OxRAM memory cell. An evaluation of the reliability and the main memory performances in terms of Forming voltage, memory window, endurance and thermal stability were performed for each memory stack through electrical characterizations. These assessments highlighted efficient memory stacks which have been integrated into a 16Kb demonstrator. Finally, a study of the variability of the resistive states as well as their degradation mechanisms during the endurance and thermal stability were carried out through simples models and atomistic simulations (ab-initio calculations)
Méthodologie d'évaluation de la sensibilité des microprocesseurs vis à vis des rayonnements cosmiques. by Sabrine Houssany( )

1 edition published in 2013 in French and held by 2 WorldCat member libraries worldwide

Les circuits électroniques embarqués dans les systèmes évoluant au niveau spatial ou dans l'atmosphère sont soumis à des particules naturellement présentes qui peuvent provoquer une perturbation de leur fonctionnement. Le type d'effet lié à ces particules le plus souvent rencontré dans les composants logiques est le SEU. Cet effet correspond à l'inversion de l'état logique d'un élément de mémorisation. De nombreuses études ont été menées pour mettre au point des outils et méthodologies permettant de caractériser la sensibilité des mémoires (SRAM principalement) vis-à-vis de ce type d'effets. Néanmoins, avec l'augmentation importante de l'électronique embarquée et plus particulièrement, l'utilisation de composants de plus en plus complexes comme les microprocesseurs multicoeurs, il est devenu difficile, à l'aide des outils jusque là disponibles, de déterminer l'impact réel d'une erreur déclenchée dans un élément de mémorisation sur une application exécutée par le système électronique. L'utilisation des outils et méthodologies actuellement disponibles ne constituent alors qu'une approche pire cas : tous les éléments de mémorisation non protégés du composant sont comptabilisés et considérés comme sensibles, ce qui amène à considérer des marges importantes lors de l'analyse de risque de l'équipement. Une réduction importante de ces marges est possible en analysant le comportement dynamique de l'application opérée par le composant complexe. En effet, tous les éléments de mémorisation ne sont pas sensibles 100% du temps et de nombreux mécanismes de masquage peuvent faire en sorte qu'une erreur au niveau composant n'ait pas d'incidence sur l'application. Ce sujet de thèse aboutira à la mise au point d'un outil permettant de connaitre avec plus de précisions la sensibilité réelle d'une application opérée sur un microprocesseur, en vue d'optimiser les protections nécessaires et plus particulièrement, de tirer profit de l'architecture spécifique des microprocesseurs multicoeurs. Pour réaliser cette étude, les axes suivants seront investigués : - Étude de l'architecture des microprocesseurs - Utilisation des modèles de performance de processeurs - Utilisation des techniques d'émulation par FPGA - Analyse logicielle du code de l'application Des validations expérimentales sous laser et faisceau de particules seront également réalisées
Réseaux de neurones impulsionnels basés sur les mémoires résistives pour l'analyse de données neuronales by Thilo Werner( )

1 edition published in 2017 in English and held by 2 WorldCat member libraries worldwide

The central nervous system of humankind is an astonishing information processing system in terms of its capabilities, versatility, adaptability and low energy consumption. Its complex structure consists of billions of neurons interconnected by trillions of synapses forming specialized clusters. Recently, mimicking those paradigms has attracted a strongly growing interest, triggered by the need for advanced computing approaches to tackle challenges related to the generation of massive amounts of complex data in the Internet of Things (IoT) era. This has led to a new research field, known as cognitive computing or neuromorphic engineering, which relies on the so-called non-von-Neumann architectures (brain-inspired) in contrary to von-Neumann architectures (conventional computers). In this thesis, we explore the use of resistive memory technologies such as oxide vacancy based random access memory (OxRAM) and conductive bridge RAM (CBRAM) for the design of artificial synapses that are a basic building block for neuromorphic networks. Moreover, we develop an artificial spiking neural network (SNN) based on OxRAM synapses dedicated to the analysis of spiking data recorded from the human brain with the goal of using the output of the SNN in a brain-computer interface (BCI) for the treatment of neurological disorders. The impact of reliability issues characteristic to OxRAM on the system performance is studied in detail and potential ways to mitigate penalties related to single device uncertainties are demonstrated. Besides the already well-known spike-timing-dependent plasticity (STDP) implementation with OxRAM and CBRAM which constitutes a form of long term plasticity (LTP), OxRAM devices were also used to mimic short term plasticity (STP). The fundamentally different functionalities of LTP and STP are put in evidence
Caractérisation et conception d' architectures basées sur des mémoires à changement de phase by Athanasios Kiouseloglou( )

1 edition published in 2015 in English and held by 2 WorldCat member libraries worldwide

Semiconductor memory has always been an indispensable component of modern electronic systems. The increasing demand for highly scaled memory devices has led to the development of reliable non-volatile memories that are used in computing systems for permanent data storage and are capable of achieving high data rates, with the same or lower power dissipation levels as those of current advanced memory solutions.Among the emerging non-volatile memory technologies, Phase Change Memory (PCM) is the most promising candidate to replace conventional Flash memory technology. PCM offers a wide variety of features, such as fast read and write access, excellent scalability potential, baseline CMOS compatibility and exceptional high-temperature data retention and endurance performances, and can therefore pave the way for applications not only in memory devices, but also in energy demanding, high-performance computer systems. However, some reliability issues still need to be addressed in order for PCM to establish itself as a competitive Flash memory replacement.This work focuses on the study of embedded Phase Change Memory in order to optimize device performance and propose solutions to overcome the key bottlenecks of the technology, targeting high-temperature applications. In order to enhance the reliability of the technology, the stoichiometry of the phase change material was appropriately engineered and dopants were added, resulting in an optimized thermal stability of the device. A decrease in the programming speed of the memory technology was also reported, along with a residual resistivity drift of the low resistance state towards higher resistance values over time.A novel programming technique was introduced, thanks to which the programming speed of the devices was improved and, at the same time, the resistance drift phenomenon could be successfully addressed. Moreover, an algorithm for programming PCM devices to multiple bits per cell using a single-pulse procedure was also presented. A pulse generator dedicated to provide the desired voltage pulses at its output was designed and experimentally tested, fitting the programming demands of a wide variety of materials under study and enabling accurate programming targeting the performance optimization of the technology
Test et diagnostic de défauts dans les interconnexions métalliques des circuits numériques par infrastructures "IP" by Lionel Forli( Book )

2 editions published in 2005 in French and held by 2 WorldCat member libraries worldwide

La problématique de ce sujet se focalise sur les interconnexions métalliques intervenant dans les circuits numériques, de façon à répondre, d'une part, à l'augmentation des produits logiques, mais d'autre part, à plus de la majorité des étapes du procédé de fabrication. La complexité des circuits et du procédé de fabrication associée à l'amélioration des rendements nécessite le développement de nouveaux outils de test et de diagnostic afin de favoriser la rapidité et la rentabilité du test et des analyses. Ces outils conservent les avantages d'une corrélation entre la conception, la fabrication et le test, tout en s'orientant vers les technologies de systèmes sur puces. Ainsi, l'utilisation de structures sous forme d'infrastructures "IP" est inévitable. Notre approche de test et de diagnostic de défauts s'est basée sur l'obtention de signatures électriques représentatives des divers états de défaillances. Ensuite, plusieurs simulations ont permis de créer ou générer dynamiquement un dictionnaire de fautes pour le diagnostic de défaillances. Une première infrastructure "IP", dont la structure matricielle redimensionnable permet une insertion comme PCM ou comme bloc "IP", diagnostique les défauts critiques dans les interconnexions par l'utilisation d'outils d'analyse et de visualisation des signatures de défauts. L'architecture d'une seconde infrastructure "IP", basée sur la fusion de cellules mémoires "SRAM" et d'oscillateurs en anneau, permet le diagnostic de défauts critiques et paramétriques globaux mais aussi la caractérisation de défauts paramétriques locaux par l'utilisation de modèles mathématiques de signatures électriques obtenues par transformée de Fourier
Emerging 3D technologies for efficient implementation of FPGAs by Ogun Turkyilmaz( )

1 edition published in 2014 in English and held by 2 WorldCat member libraries worldwide

La complexité croissante des systèmes numériques amène les architectures reconfigurable telles que les Field Programmable Gate Arrays (FPGA) à être très fortement demandés en raison de leur facilité de (re)programmabilité et de leurs faibles coûts non récurrents (NRE). La re-configurabilité est réalisée grâce à de nombreux point mémoires de configuration. Cette re-configurabilité se traduit par une extrême flexibilité des applications implémentées et dans le même temps par une perte en surface, en performances et en puissance par rapport à des circuits intégrés spécifiques (ASIC) pour la même fonctionnalité. Dans cette thèse, nous proposons la conception de FPGA avec différentes technologies 3D pour une meilleure efficacité. Nous intégrons les blocs à base de mémoire résistives pour réduire la longueur des fils de routage et pour élargir l'employabilité des FPGAs pour des applications non-volatiles de faible consommation. Parmi les nombreuses technologies existantes, nous nous concentrons sur les mémoires à base d'oxyde résistif (OxRRAM) et les mémoires à pont conducteur (CBRAM) en évaluant les propriétés uniques de ces technologies. Comme autre solution, nous avons conçu un nouveau FPGA avec une intégration monolithique 3D (3DMI) en utilisant des interconnexions haute densité. A partir de deux couches avec l'approche logique-sur-mémoire, nous examinons divers schémas de partitionnement avec l'augmentation du nombre de couches actives intégrées pour réduire la complexité de routage et augmenter la densité de la logique. Sur la base des résultats obtenus, nous démontrons que plusieurs niveaux 3DMI est une alternative solide pour l'avenir de mise à l'échelle de la technologie
Caractérisation électrique et modélisation de la dynamique de commutation résistive dans des mémoires OxRAM à base de HfO2 by Clément Nguyen( )

1 edition published in 2018 in French and held by 2 WorldCat member libraries worldwide

Oxyde-based resistive memories OxRAM are a technology of emergent non-volatile memory, as phase-change memories (PCRAM) or magnetoresistive memories (MRAM). In the beginning OxRAM were very studied in order to compete with Flash memories, whose mechanism relies on the storage of electrical charges in a flotting gate. However, with the arising of 3D-NAND technology, it seems very difficult for OxRAM to reach the same storage capacities as Flash memories. But their impressive operating speed, far higher than NAND's, and their cost far lower than DRAM's, allow them to operate at the border of these two technologies, in a category called « Storage Class Memory ». Furthermore, the integration of OxRAM in the Back-End-Of-Line, just above CMOS circuits, makes this technology very attractive. On the other hand, OxRAM are known to have a very strong variability, which represents the main obstacle to their expansion.In this thesis, the dynamics of the resistive switching of hafnium oxyde based OxRAM has been investigated, with a desire to focus on very short times, as they are one of the main assets of this technology. To do so, our work first focuses on an experimental aspect, with electrical characterization. We were able to watch, with a dynamical monitoring, the resistive switching of the memories, at the scale of the dozen of nanoseconds, for writing and erasing operations, thanks to an entirely dedicated set-up. Then, the impacts that the time reduction, and the lowering of the voltage and current, can have on the reliability of OxRAM, were analysed, with variability measurements. The second part of this work concerns modelisation, with the elaboration of a physics-based, semi-analytical model, in order to understand the switching mechanisms. After the comparison of the results obtained by our model with the experimental ones, our model has been applied to statistical measurements. Electrical tests on OxRAM arrays have been performed, and fitted by the model. Finally, the low frequency noise (RTN) in OxRAM has been studied, as it stands as one of the main factors of degradation of OxRAM reliability. Ideas to improve the robustness of OxRAM against RTN are suggested
Conception de SRAM ultra basse tension à haute efficacité énergétique basé sur de nouvelles technologies pour les applications IoT by Réda Boumchedda( )

1 edition published in 2019 in English and held by 2 WorldCat member libraries worldwide

The main constraint related to the IoT applications, is the low power consumption required withoutnecessarily compromising with the performance. Driven by the fast IoT market expansion, thearchitecture of the IoT nodes are evolving to best answer these constraints and propose the besttrade-off between the performance and the power consumption. The SRAM embedded in IoT nodecontributes greatly to the power consumption and is the bottleneck of performance. Therefore,optimizing their design is a priority. This thesis research work proposes different SRAM designs inthe context of an IoT node architecture using asynchronous logic to elevate the powerconsumption/performance trade-off.A single-rail TP SRAM is designed in 28nm FD-SOI technology specifically for asynchronous/asynchronous IoT node. This SRAM supports an asynchronous interfacecommunication and a fast transition sleep/active mode. This SRAM enables simultaneoussynchronous and asynchronous accesses on its two independent ports, as well as a selective virtualground (SVGND) to support ultra-low voltage in read operations. Measurements on a 64kbitsmemory macro prove the functionality for a supply voltage ranging from 0.25V to 1.25V. The sleepmode enables 158x reduction of the SVGND static-power consumption. The SVGND read assistachieves a gain of 50mV on the read port operations lowest voltage. The memory achieves, at 0.25Vand 27°C, an average energy cost per access of 1.45fJ/bit at 451kHz and a leakage of 25pW/bit insleep mode.To optimize the density of the SRAM, a 4T SRAM bitcell enhanced for both write and readoperations is proposed. The proposed bitcell is designed to respond to the requirements of energyconstrained systems, as in the case of most IoT-oriented circuits and applications. The use of 3DCoolCubeTM technology enables the design of a stable 4T SRAM bitcell by using data-dependentback bias (DDBB) and allows to enhance the density of SRAMs. The proposed bitcell architectureprovides a major reduction of the write operation energy consumption compared to a conventional6T bitcell. The SVGND assist ensures a full functionality at ultra-low voltage of read operations.Simulation results show reliable operations down to 0.35V close to six sigma (6ó) without any writeassist techniques (e.g. negative bitlines). The 4T bitcell achieves in worst case corner 300ns and125ns in write and read access time, respectively. A 6x energy consumption reduction compared toa low voltage/low leakge 6T bitcell is demonstrated.This thesis work resulted in several publications, a patent and a silicon implementation withvalidated results
Etude et intégration de mémoires résistives 3D pour application haute densité by Giuseppe Piccolboni( )

1 edition published in 2016 in English and held by 2 WorldCat member libraries worldwide

The scope of the thesis was to characterize and help further development of the first LETI-fabricated vertical resistive RAM (VRRAM). Among emerging memories Resistive RAMs (ReRAM) seems promising in terms of scalability, switching speed, fabrication costs and ease of production. As in the case of FLASH devices, which are attaining their physical limits in terms of scalability, resistive memories are already being studied in vertical geometry in order to propose solutions that maximize memory density. This work proceeded as follows: at first 1 Resistor (1R) devices were characterized to gain a general understanding of the memory cells functioning and to perform the first screening in terms of stack composition and thicknesses. Once the best configurations were identified 1 Transistor- 1 Resistor (1T-1R) devices were integrated in order to assess memory performances in an industrial-like fashion. 1R devices were integrated in a MESA structure while 1T-1R devices were integrated in both MESA and VIA architectures. In both architectures the memory cell is found on the sidewall of the structure; particularly challenging was the deposition of the top electrode. Devices were electrically characterized to extract the following information: initial resistance, forming, set and reset voltages, switching times, high and low resistance states (HRS and LRS) resistances, endurance characteristics and data retention times. This set of measurements allowed to extensively study the capability of VRRAM as a non-volatile memory candidate. It was shown that HfO2-based VRRAM have 107 endurance capability for a set current (ISET) of 300 [µA], more than 105 [s] data retention for a SET current of 100 [µA] at 200 [˚C] backing temperature and down to 20 [ns] switching time. ISET was also reduced down to 7 [µA] and memory cell showed switching capability although the conductive filament (CF) resulted unstable after data retention tests. Experimental results obtained were in accordance with previous studies conducted on planar devices showing that vertical geometry did not have a significant effect on memory behavior. Finally 2-level memory devices were fabricated. These samples were really useful to perform important tests for future high density integration: the 2 level devices were compared in terms of switching voltages and resistances to verify the reproducibility of the integration along the sidewall of the structure. Disturb tests were carried out to be sure that write/erase operations on one level did not influence the state of the un-selected level. Another part of the thesis was dedicated to the physical investigation of the conducting filament behavior during cycling. This study showed that a correlation exists among resistances while cycling. In order to explain these measurements both analytical and physical models were proposed. Both rely on the assumption that there is a parameter during cycling that is related to its previous values; in the case of the analytical model this parameter is simply the resistance while in the physical model the parameter is the CF gap (LGAP). Both models show good fit with experimental data suggesting therefore that at any given cycle the morphology of the conductive filament is dependent on the morphology during the previous cycles. Another part of the thesis was also dedicated to a study on high density applications:starting from the electrical results obtained on 2-level VRRAM and supposing to work with an integrated selector the maximum array size attainable was calculated as a function of various parameters such as the node half pitch, the plane thicknesses and the number of integrated levels. Finally neuromorphic applications were investigated and a VRRAM pillar was proposed as a synapse emulator. VRRAMs can act as synapses in two ways: using the intrinsic probability of the ReRAM technology or programming each VRRAM cell in the pillar with a probability given from an external circuit
Analyse de robustesse de systèmes intégrés numériques by Kais Chibani( )

1 edition published in 2016 in French and held by 2 WorldCat member libraries worldwide

Les circuits intégrés ne sont pas à l'abri d'interférences naturelles ou malveillantes qui peuvent provoquer des fautes transitoires conduisant à des erreurs (Soft errors) et potentiellement à un comportement erroné. Ceci doit être maîtrisé surtout dans le cas des systèmes critiques qui imposent des contraintes de sûreté et/ou de sécurité. Pour optimiser les stratégies de protection de tels systèmes, il est fondamental d'identifier les éléments les plus critiques. L'évaluation de la criticité de chaque bloc permet de limiter les protections aux blocs les plus sensibles. Cette thèse a pour objectif de proposer des approches permettant d'analyser, tôt dans le flot de conception, la robustesse d'un système numérique. Le critère clé utilisé est la durée de vie des données stockées dans les registres, pour une application donnée. Dans le cas des systèmes à base de microprocesseur, une approche analytique a été développée et validée autour d'un microprocesseur SparcV8 (LEON3). Celle-ci repose sur une nouvelle méthodologie permettant de raffiner les évaluations de criticité des registres. Ensuite, une approche complémentaire et plus générique a été mise en place pour calculer la criticité des différents points mémoires à partir d'une description synthétisable. L'outil mettant en œuvre cette approche a été éprouvé sur des systèmes significatifs tels que des accélérateurs matériels de chiffrement et un système matériel/logiciel basé sur le processeur LEON3. Des campagnes d'injection de fautes ont permis de valider les deux approches proposées dans cette thèse. En outre, ces approches se caractérisent par leur généralité, leur efficacité en termes de précision et de rapidité, ainsi que leur faible coût de mise en œuvre et leur capacité à ré-exploiter les environnements de validation fonctionnelle
Conception et simulation des circuits numériques en 28nm FDSOI pour la haute fiabilité by Ajith Sivadasan( )

1 edition published in 2018 in English and held by 2 WorldCat member libraries worldwide

Scaling of classical CMOS technology provides an increase in performance of digital circuits owing to the possibility of incorporation of additional circuit components within the same silicon area. 28nm FDSOI technology from ST Microelectronics is an innovative scaling strategy maintaining a planar transistor structure and thus provide better performance with no increase in silicon chip fabrication costs for low power applications. It is important to ensure that the increased functionality and performance is not at the expense of decreased reliability, which can be ensured by meeting the requirements of international standards like ISO26262 for critical applications in the automotive and industrial settings. Semiconductor companies, to conform to these standards, are thus required to exhibit the capabilities for reliability estimation at the design conception stage most of which, currently, is done only after a digital circuit has been taped out. This work concentrates on Aging of standard cells and digital circuits with time under the influence of NBTI degradation mechanism for a wide range of Process, Voltage and Temperature (PVT) variations and aging compensation using backbiasing. One of the principal aims of this thesis is the establishment of a reliability analysis infrastructure consisting of software tools and gate level aging model in an industrial framework for failure rate estimation of digital circuits at the design conception stage for circuits developed using ST 28nm FDSOI technology
Conception et développement de circuits logiques de faible consommation et fiables basés sur des jonctions tunnel magnétiques à écriture par transfert de spin by Erya Deng( )

1 edition published in 2017 in English and held by 2 WorldCat member libraries worldwide

With the shrinking of CMOS (complementary metal oxide semi-conductor) technology, static and dynamic power increase dramatically and indeed has become one of the main challenges due to the increasing leakage current and long transfer distance between memory and logic chips. In the past decades, spintronics devices, such as spin transfer torque based magnetic tunnel junction (STT-MTJ), are widely investigated to overcome the static power issue thanks to their non-volatility. Hybrid logic-in-memory (LIM) architecture allows spintronics devices to be fabricated over the CMOS circuit plane, thereby reducing the transfer latency and the dynamic power dissipation. This thesis focuses on the design of hybrid MTJ/CMOS logic circuits and memories for low-power computing system.By using a compact MTJ model and the STMicroelectronics design kit for regular CMOS design, we investigate the hybrid MTJ/CMOS circuits for single-bit and multi-bit reading and writing. Optimization methods are also introduced to improve the reliability, which is extremely important for logic circuits where error correction blocks cannot be easily embedded without sacrificing their performances or adding extra area to the circuit. We extend the application of multi-context hybrid MTJ/CMOS structure to the memory design. Magnetic random access memory (MRAM) with simple peripheral circuits is designed.Based on the LIM concept, non-volatile logic/arithmetic circuits are designed to integrate MTJs not only as storage elements but also as logic operands. First, we design and theoretically analyze the non-volatile logic gates (NVLGs) including NOT, AND, OR and XOR. Then, 1-bit and 8-bit non-volatile full-adders (NVFAs), the basic elements for arithmetic operations, are proposed and compared with the traditional CMOS-based full-adder. The effect of CMOS transistor sizing and the MTJ parameters on the performances of NVFA is studied. Furthermore, we optimize the NVFA from two levels. From the structure-level, an ultra-high reliability voltage-mode sensing circuit is used to store the operand of NVFA. From the device-level, we propose 3-terminal MTJ switched by spin-Hall-assisted STT to replace the 2-terminal MTJ because of its smaller writing time and power consumption. Based on the NVLGs and NVFAs, other logic circuits can be built, for instance, non-volatile subtractor.Finally, non-volatile content addressable memory (NVCAM) is proposed. Two magnetic decoders aim at selecting a word line to be read or written and saving the corresponding search location in non-volatile state
Development of Experimental Methodology for Improved Local Variability Assessment in Advanced CMOS Devices by Omar, Jonani Franco( )

1 edition published in 2016 in English and held by 2 WorldCat member libraries worldwide

Microelectronic systems and their applications are everywhere in the current human civilization, from the simplest gadget in our everyday life to fiction-like space probes which let us see wonderful pictures of other worlds within the Solar System and beyond. The semiconductor industry has become, since its inception in the 1960s, one of the largest and growing industries with approximately a 350 billion dollars market.The central device of microelectronics is the transistor, which has experienced enormous improvements in the last half century, boosted by the economic and human investments to follow the so-called “Moore's law”, which states that the number of transistors in a chip doubles every two years. Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) has become the preferred transistor in the industry for digital applications. With the miniaturization of the transistor, a major challenge is to deal with transistor Variability, as its impact becomes more and more important with decreasing size. Two identically fabricated transistors may present highly different characteristics; when this Variability is systematic in nature, we can often find a way to eliminate it using fabrication means or model it very accurately; nevertheless, Statistical Variability is the other major component of Local Variability which is more complicated to deal with; in fact, Statistical Variability is random in nature, as it results from de granular nature of matter and also from the difficulty of control atom per atom placement in an industrial level. Then, it becomes necessary to precisely characterize and model Local Statistical Variability for Variability-aware design to better predict circuit fails from simple standard circuits to final products.The purpose of this project is to go further in the characterization means of MOSFET Local Variability by revisiting existing test structures, and to develop methods of analysis to extract the maximum of relevant information about transistor Variability sources and impact from experiments conducted on improved test structures. One important merit for the Variability characterization methods developed in this project is to enable an accurate statistical modeling of Local Variations and their impact throughout the design space; to meet the goal, the methods developed must provide statistical parameters with well-established confidence, and be suited for implementation on statistical models within the circuit design flow.To achieve this objective, this work is a common project of STMicroelectronics and IMEP-LAHC laboratory, which benefit from access to 28 nm silicon technology home design test structures and state-of-the-art characterization facilities.The project is primarily focused on local variability (in micrometer scale and below), whether of systematic or statistical nature. Nevertheless, some aspects of Intrawafer and Systematic Variations are studied when it is necessary to discriminate Local Variability from other effects
Optimisation de l'efficacité énergétique des applications numériques en technologie FD-SOI 28-14nm by Bertrand Pelloux-Prayer( )

1 edition published in 2014 in French and held by 2 WorldCat member libraries worldwide

Over the last ten years, the scaling of MOSFETs in bulk planar technology is experiencing a significant increase in parasitic phenomenon driven by the reduction of the transistor channel length. These short-channel effects lead to the degradation of transistor performances, making circuits less energy efficient and more sensitive to the manufacturing process fluctuations. Therefore, this technology faces a real barrier for nodes beyond 32nm.To meet the needs of mobile devices, combining high performances and low power consumption, the planar fully depleted silicon-on-insulator (FD-SOI) technology appears to be a suitable solution. Indeed, thanks to its thin-film of silicon and an undoped channel, MOS transistors have an excellent short-channel electrostatic control and a low variability of the threshold voltage given by an immunity to random dopant fluctuation. In addition, this compelling technology enables to adjust the threshold voltage of transistors by applying a wide ±3V back-bias voltage on Wells. Thus, this specific FD-SOI feature brings to IC designers an additional lever to modulate the performance and to optimize the energy efficiency of circuits.The research work presented in this thesis has contributed to the development of FD-SOI technology platform for the 28 and 14nm nodes. Initially, a critical path extracted from an ARM Cortex-A9 processor was used to assess both the intrinsic gains provided by the FD-SOI technology and those produced by modulating the back-bias voltages. This technique enables to divide by up to 50 times the static current of circuits in standby mode, or by 2 the total energy consumption at same frequency. In the second phase, several design solutions are proposed in order to optimize the energy efficiency of circuits again. Among these, the design of a single-Well structure enables to solve the conventional multi-VT co-integration issue, occurring in FD-SOI. Moreover, this novel approach also offers an efficient solution for integrated circuits operating over a wide supply voltage range. Indeed, thanks to a single back-bias voltage, both n and p-MOS transistors could be easily balanced enabling an outstanding minimal supply voltage
Contribution à l'évaluation de la technique de génération d'harmonique par faisceau laser pour la mesure des champs électriques dans les circuits intégrés (EFISHG) by Thomas Fernandez( )

1 edition published in 2009 in French and held by 1 WorldCat member library worldwide

Ce travail contribue à l'évaluation de la technique de génération de seconde harmonique induite par un champ électrique quasi statique, ou technique EFISHG, appliquée au domaine de la microélectronique. Une description du principe de la technique EFISHG, basé sur l'optique non linéaire, permet d'appréhender l'origine physique de cette méthode. Un état de l'art a permis d'identifier deux champs d'applications liés à la microélectronique : l'analyse de défaillance, via la mesure en temps de réelle des variations de champs électriques internes dans les circuits intégrés, et la fiabilité par l'étude du piégeage de charges à l'interface Si/SiO2 et de la dégradation dite de « Negative Bias Temperature Instability » ou NBTI. Ce manuscrit présente les différentes étapes qui ont permis l'élaboration d'un banc de test en vue de l'évaluation de l'applicabilité de la technique EFISHG à ces problématiques. Les résultats expérimentaux obtenus avec ce montage ont permis de mettre en avant les possibilités qu'offre la technique EFISHG à caractériser et à accélérer le vieillissement NBTI
Rétro-conception matérielle partielle appliquée à l'injection ciblée de fautes laser et à la détection efficace de Chevaux de Troie Matériels by Franck Courbon( )

1 edition published in 2015 in French and held by 1 WorldCat member library worldwide

The work described in this thesis covers an integrated circuit characterization methodology based on a partial hardware reverse engineering. On one hand in order to improve integrated circuit security characterization, on the other hand in order to detect the presence of Hardware Trojans. Our approach is said partial as it is only based on a single hardware layer of the component and also because it does not aim to recreate a schematic or functional description of the whole circuit. A low cost, fast and efficient reverse engineering methodology is proposed. The latter enables to get a global image of the circuit where only transistor's active regions are visible. It thus allows localizing every standard cell. The implementation of this methodology is applied over different secure devices. The obtained image according to the methodology declined earlier is processed in order to spatially localize sensible standard cells, nay critical in terms of security. Once these cells identified, we characterize the laser effect over different location of these standard cells and we show the possibility with the help of laser fault injection the value they contain. The technique is novel as it validates the fault model over a complex gate in 90nm technology node.Finally, a Hardware Trojan detection method is proposed using the partial reverse engineering output. We highlight the addition of few non listed cells with the application on a couple of circuits. The method implementation therefore permits to detect, without full reverse-engineering (and so cheaply), quickly and efficiently the presence of Hardware Trojans
Prise en compte de la variabilité dans l'étude et la conception de circuits de lecture pour mémoires résistives by Salmen Mraihi( )

1 edition published in 2018 in English and held by 1 WorldCat member library worldwide

Nowadays, Systems on chip (SoCs) conception is becoming more and more complex and demand an ever-increasing amount of memory capacity. This leads to aggressive bit cell technology scaling. Nonvolatile resistive memories (PC-RAM, RRAM, MRAM) are promising technologic alternatives to ensure both high density, low power consumption, low area and low latencies. However, scaling lead to significant memory cell and/or memory periphery variability. This thesis aims to address variability issues in read circuitries of resistive memories and propose solutions for read yield enhancement of these memories. To this end, several sub-studies were achieved: overall review of the existing solutions for read yield enhancement, at both circuit and system level; development of a statistical model evaluating the contributions to read margin of the variability of each component of the resistive memory sensing path; analysis, characterization modelling and optimization of the offset of one particular dynamic sense amplifier for resistive memories; proposal of a sense amplifier architecture that features an optimum signal to offset ratio
Méthodologie et développement de solutions pour la sécurisation des circuits numériques face aux attaques en tensions by Kamil Gomina( )

1 edition published in 2014 in French and held by 1 WorldCat member library worldwide

Les applications grand public comme la téléphonie mobile ou les cartes bancaires manipulent des données confidentielles. A ce titre, les circuits qui les composent font de plus en plus l'objet d'attaques qui présentent des menaces pour la sécurité des données. Les concepteurs de systèmes sur puce (SoC) doivent donc proposer des solutions sécurisées, tout en limitant le coût et la complexité globale des applications. L'analyse des attaques existantes sur les circuits numériques nous a orienté vers celles se basant sur la tension d'alimentation, dans des nœuds technologiques avancés.Dans un premier temps, nous avons déterminé la signature électrique d'un circuit en phase de conception. Pour cela, un modèle électrique a été proposé, prenant en compte la consommation en courant et la capacité de la grille d'alimentation. L'extraction de ces paramètres ainsi que l'évaluation du modèle sont présentées. L'utilisation de ce modèle a permis de mesurer la vulnérabilité d'un circuit mais aussi d'évaluer quantitativement des contremesures, notamment celle utilisant des capacités de découplage. Ensuite, l'étude se consacre à l'injection de fautes par impulsions de tension d'alimentation. Les mécanismes d'injection de fautes sur des circuits numériques ont été étudiés. Dès lors, des solutions de détection d'attaques ont été proposées et évaluées à la fois en simulation et par des tests électriques sur circuit. Les résultats ont permis de confirmer les analyses théoriques et la méthodologie utilisée.Ce travail a ainsi montré la faisabilité de solutions à bas coût contre les attaques actives et passives en tension, utilisables dans le cadre d'un développement industriel de produits
Evaluation des futures technologies CMOS (Inférieure à 50 nm) au niveau circuit by Manuel Sellier( Book )

1 edition published in 2008 in French and held by 1 WorldCat member library worldwide

The goal of this study is to perform circuit level assessment of future CMOS technologies. To this end, predictive design kits have been made. These kits rely on future devices and interconnect modeling, and on the digital flow tools parameter setting in the framework of future technologies. The results of the evaluations carried out thanks to these kits show a drastic increase of interconnect delays suggesting that there will be an important issue of repeater adding for the future circuits. In the short run (32nm), the evaluation led with the predictive design flow show that the interconnect delay problem do not seem to play an important role for small blocs. Concerning the variability of the devices which affect all particularly circuits such as SRAM memories, stagnation at non acceptable levels is highlighted although solutions consisting in using undoped devices are identified. The worth use of a new SRAM memory consisting of using undoped devices for NMOS transistors only is also shown
 
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