WorldCat Identities

Tisserand, Arnaud (19..-....; chercheur en informatique)

Overview
Works: 23 works in 26 publications in 2 languages and 32 library holdings
Roles: Other, Thesis advisor, Opponent, Publishing director, Author
Publication Timeline
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Most widely held works by Arnaud Tisserand
Architecture des ordinateurs( Book )

1 edition published in 2013 in French and held by 3 WorldCat member libraries worldwide

Adequation arithmetique architecture. Problemes et etude de cas by Arnaud Tisserand( Book )

2 editions published in 1997 in French and held by 2 WorldCat member libraries worldwide

LES MACHINES ACTUELLES OFFRENT DE PLUS EN PLUS DE FONCTIONNALITES ARITHMETIQUES AU NIVEAU MATERIEL. LES GENERATIONS ACTUELLES DE PROCESSEURS PROPOSENT DES OPERATEURS MATERIELS RAPIDES POUR LE CALCUL DES DIVISIONS, DES RACINES CARREES, DES SINUS, DES COSINUS, DES LOGARITHMES... LA LITTERATURE DU DOMAINE MONTRE QU'EN CHANGEANT NOTRE FACON DE REPRESENTER LES NOMBRES ET/OU EN UTILISANT DES ALGORITHMES SPECIFIQUES DE CALCUL, IL EST POSSIBLE DE REALISER DES OPERATEURS MATERIELS PARTICULIEREMENT EFFICACES. LE BUT DE CETTE THESE EST D'ETUDIER ET D'ILLUSTRER LES LIENS PROFONDS EXISTANTS ENTRE L'ARITHMETIQUE ET L'ARCHITECTURE DES ORDINATEURS A TRAVERS QUATRE PROBLEMES. LES OPERATEURS ARITHMETIQUES ASYNCHRONES PERMETTENT DE CALCULER LES FONCTIONS ARITHMETIQUES (ADDITION, MULTIPLICATION, DIVISION) AVEC UN DELAI VARIABLE. EN PARTICULIER, NOUS AVONS DEVELOPPE UN ADDITIONNEUR ASYNCHRONE DONT LE TEMPS MOYEN DE CALCUL EST O(LOG N). L'ARITHMETIQUE EN-LIGNE PERMET DE REALISER DES ARCHITECTURES OU LES NOMBRES CIRCULENT EN SERIE, CHIFFRE PAR CHIFFRE, LES POIDS FORTS EN TETE. L'INTERET DE CETTE ARITHMETIQUE EST DE POUVOIR CALCULER TOUTES LES FONCTIONS (EN ARITHMETIQUE SERIE POIDS FAIBLES EN TETE, IL N'EST PAS POSSIBLE DE CALCULER LES DIVISIONS ET LES RACINES CARREES) ET D'OBTENIR DES OPERATEURS DE PETITE TAILLE AVEC UN NOMBRE D'ENTREES/SORTIES PLUS FAIBLE QUE LEUR EQUIVALENTS PARALLELES. L'ARRONDI EXACT DES FONCTIONS ELEMENTAIRES CONSISTE A DETERMINER LA PRECISION INTERMEDIAIRE PERMETTANT DE TOUJOURS POUVOIR ARRONDIR EXACTEMENT LES RESULTATS DU CALCUL DES FONCTIONS ELEMENTAIRES (SINUS, COSINUS, EXPONENTIELLE...). NOUS PROPOSONS DANS CETTE THESE UNE METHODE QUI PERMET D'ARRONDI EXACTEMENT LES FONCTIONS ELEMENTAIRES ASSEZ RAPIDEMENT. LE SYSTEME SEMI-LOGARITHMIQUE DE REPRESENTATION DES NOMBRES EST UN SYSTEME PERMETTANT D'EFFECTUER RAPIDEMENT LES CALCULS DE PROBLEMES DONT LE NOMBRE DE MULTIPLICATIONS/DIVISIONS EST GRAND DEVANT LE NOMBRE D'ADDITIONS/SOUSTRACTIONS
Opérateurs arithmétiques matériels pour des applications spécifiques by Nicolas Veyrat-Charvillon( Book )

2 editions published in 2007 in French and held by 2 WorldCat member libraries worldwide

Computer arithmetic is a branch of computer science dedicated to number systems, arithmetic algorithms and their hardware and software implementations. This thesis deals with the study and hardware implementation of operators for the evaluation of functions for specific applications in digital signal and image processing and in cryptography. The first part introduces operators for function evaluation that are based on polynomial approximations that require little hardware. The second part studies the automatic generation of shift-and-add operators (SRT-like) for the evaluation of some algebraic functions. The last part presents an effective and compact implementation of the SHA-2 family of cryptographic hash functions. The various operators proposed in this thesis have been validated on FPGA circuits
Sécurisation matérielle pour la cryptographie à base de courbes elliptiques by Simon Pontie( )

1 edition published in 2016 in French and held by 2 WorldCat member libraries worldwide

Many applications require achieving high security level (confidentiality or integrity). My thesis is about hardware acceleration of asymmetric cryptography based on elliptic curves (ECC). These systems are rarely in a controlled environment. With this in mind, I consider potential attackers with physical access to the cryptographic device.In this context, a very flexible crypto-processor was developed that can be implemented as an ASIC or on FPGAs. To choose protections against physical attacks (power consumption analysis, fault injection, etc), I evaluate the security against side-channel attacks and the cost of the counter-measure based on operation unification. By mounting a new attack against a chip using Jacobi quartic curves, I show that re-using operands is detectable. By exploiting only some power consumption traces, I manage to recover the secret. I present also a new counter-measure allowing finding a compromise between security level, performances, and overheads. It uses random windows to accelerate computation, mixed to an optimized usage of dummy operations
FLIP, a floating-point library for integer processors by Saurabh-Kumar Raina( Book )

2 editions published in 2006 in English and held by 2 WorldCat member libraries worldwide

Design, Optimization, and Formal Verification of Circuit Fault-Tolerance Techniques by Dmitry Burlyaev( )

1 edition published in 2015 in English and held by 2 WorldCat member libraries worldwide

La miniaturisation de la gravure et l'ajustement dynamique du voltage augmentent le risque de fautes dans les circuits intégrés. Pour pallier cet inconvénient, les ingénieurs utilisent des techniques de tolérance aux fautes pour masquer ou, au moins, détecter les fautes. Ces techniques sont particulièrement utilisées dans les domaines critiques (aérospatial, médical, nucléaire, etc.) où les garanties de bon fonctionnement des circuits et leurs tolérance aux fautes sont cruciales. Cependant, la vérification de propriétés fonctionnelles et de tolérance aux fautes est un problème complexe qui ne peut être résolu par simulation en raison du grand nombre d'exécutions possibles et de scénarios d'occurrence des fautes. De même, l'optimisation des surcoûts matériels ou temporels imposés par ces techniques demande de garantir que le circuit conserve ses propriétés de tolérance aux fautes après optimisation.Dans cette thèse, nous décrivons une optimisation de techniques de tolérance aux fautes classiques basée sur des analyses statiques, ainsi que de nouvelles techniques basées sur la redondance temporelle. Nous présentons comment leur correction peut être vérifiée formellement à l'aide d'un assistant de preuves.Nous étudions d'abord comment certains voteurs majoritaires peuvent être supprimés des circuits basés sur la redondance matérielle triple (TMR) sans violer leurs propriétés de tolérance. La méthodologie développée prend en compte les particularités des circuits (par ex. masquage logique d'erreurs) et des entrées/sorties pour optimiser la technique TMR.Deuxièmement, nous proposons une famille de techniques utilisant la redondance temporelle comme des transformations automatiques de circuits. Elles demandent moins de ressources matérielles que TMR et peuvent être facilement intégrés dans les outils de CAO. Les transformations sont basées sur une nouvelle idée de redondance temporelle dynamique qui permet de modifier le niveau de redondance «à la volée» sans interrompre le calcul. Le niveau de redondance peut être augmenté uniquement dans les situations critiques (par exemple, au-dessus des pôles où le niveau de rayonnement est élevé), lors du traitement de données cruciales (par exemple, le cryptage de données sensibles), ou pendant des processus critiques (par exemple, le redémarrage de l'ordinateur d'un satellite).Troisièmement, en associant la redondance temporelle dynamique avec un mécanisme de micro-points de reprise, nous proposons une transformation avec redondance temporelle double capable de masquer les fautes transitoires. La procédure de recouvrement est transparente et le comportement entrée/sortie du circuit reste identique même lors d'occurrences de fautes. En raison de la complexité de cette méthode, la garantie totale de sa correction a nécessité une certification formelle en utilisant l'assistant de preuves Coq. La méthodologie développée peut être appliquée pour certifier d'autres techniques de tolérance aux fautes exprimées comme des transformations de circuits
Implantations et protections de mécanismes cryptographiques logiciels et matériels by Marie-Angela Cornelie( )

1 edition published in 2016 in French and held by 2 WorldCat member libraries worldwide

The protection of cryptographic mechanisms is an important challenge while developing a system of information because they allow to ensure the security of processed data. Since both hardware and software supports are used, the protection techniques have to be adapted depending on the context.For a software target, legal means can be used to limit the exploitation or the use. Nevertheless, it is in general difficult to assert the rights of the owner and prove that an unlawful act had occurred. Another alternative consists in using technical means, such as code obfuscation, which make the reverse engineering strategies more complex, modifying directly the parts that need to be protected.Concerning hardware implementations, the attacks can be passive (observation of physical properties) or active (which are destructive). It is possible to implement mathematical or hardware countermeasures in order to reduce the information leakage during the execution of the code, and thus protect the module against some side channel attacks.In this thesis, we present our contributions on theses subjects. We study and present the software and hardware implementations realised for supporting elliptic curves given in Jacobi Quartic form. Then, we discuss issues linked to the generation of curves which can be used in cryptography, and we propose an adaptation to the Jacobi Quartic form and its implementation. In a second part, we address the notion of code obfuscation. We detail the techniques that we have implemented in order to complete an existing tool, and the complexity module which has been developed
Accélérateurs matériels sécurisés pour la cryptographie post-quantique by Timo Zijlstra( )

1 edition published in 2020 in English and held by 2 WorldCat member libraries worldwide

Shor's quantum algorithm can be used to efficiently solve the integer factorisation problem and the discrete logarithm in certain groups. The security of the most commonly used public key cryptographic protocols relies on the conjectured hardness of exactly these mathematical problems. A sufficiently large quantum computer could therefore pose a threat to the confidentiality and authenticity of secure digital communication. Post quantum cryptography relies on mathematical problems that are computationally hard for quantum computers, such as Learning with Errors (LWE) and its variants RLWE and MLWE. In this thesis, we present and compare FPGA implementations of LWE, RLWE and MLWE based public key encryption algorithms. We discuss various trade-offs between security, computation time and hardware cost. The implementations are parallelized in order to obtain maximal speed-up. We show that MLWE has the best performance in terms of computation time and area utilization, and can be parallelized more efficiently than RLWE. We also discuss hardware security and propose countermeasures against side channel attacks for RLWE. We consider countermeasures from the state of the art, such as masking and blinding, and propose improvements to these algorithms. Moreover, we propose new countermeasures based on redundant number representation and the random shuffling of operations. All countermeasures are implemented on FPGA to compare their cost and computation time overhead. Our proposed protection based on redundant number representation is particularly flexible, in the sens that it can be implemented for various degrees of protection at various costs
Approche de simulation transactionnelle pour la modélisation des performances et de l'énergie d'un système mémoire pour SoC hétérogènes by Amal Ben Ameur( )

1 edition published in 2019 in English and held by 1 WorldCat member library worldwide

Mobile devices, at each new release of the standards and following users' continuous requests of new services, have to support more and more features, which are also becoming more and more demanding from the computational point of view. As a consequence, being able to fulfil new requirements and at the same time to provide power efficient chips is nowadays the most important challenge for mobile devices system designers. To tackle this challenge, novel system level performance and power modeling approaches have been proposed allowing hardware/software (HW/SW) architectures to be explored right at the very first steps of a System-on-Chip (SoC) design flow. However, existing solutions have limited support for the power optimization of the memory system (including SDRAM) that may occupy more than 70% of a chip area and consume more than 30% of the total energy. In our work, we propose a SystemC-TLM-based simulation framework at Electronic System Level (ESL), which is able to support the joint exploration of a SoC architecture and its memory configuration. This new framework helps in optimizing the SoC energy consumption while matching the required performance in terms of power and performance, as well as of memory bandwidth and latency
Etude et conception d'opérateurs arithmétiques by Arnaud Tisserand( Book )

1 edition published in 2010 in French and held by 1 WorldCat member library worldwide

Conception de matériel salutaire pour lutter contre la contrefaçon et le vol de circuits intégrés by Cédric Marchand( )

1 edition published in 2016 in French and held by 1 WorldCat member library worldwide

Le vol et la contrefaçon touchent toutes les sphères industrielles de nos sociétés. En particulier, les produits électroniques représentent la deuxième catégorie de produits la plus concernée par ces problèmes. Parmi les produits électroniques les plus touchés, on retrouve les téléphones mobiles, les tablettes, les ordinateurs mais aussi des éléments bien plus basiques comme des circuits analogiques ou numériques et les circuits intégrés. Ces derniers sont au coeur de la plupart des produits électroniques et un téléphone mobile peut être considéré comme contrefait s'il possède ne serait-ce qu'un seul circuit intégré contrefait. Le marché de la contrefaçon de circuits intégrés représente entre 7 et 10% du marché total des semi-conducteurs, ce qui implique une perte d'au moins 24 milliards d'euros en 2015 pour les entreprises concevant des circuits intégrés. Ces pertes pourraient s'élever jusqu'à 36 milliards d'euros en 2016. Il est donc indispensable de trouver des solutions pratiques et efficaces pour lutter contre la contrefaçon et le vol de circuits intégrés. Le projet SALWARE, financé par l'Agence Nationale de la Recherche et par la Fondation de Recherche pour l'Aéronautique et l'Espace, a pour but de lutter contre le problème de la contrefaçon et du vol de circuits intégrés et propose l'étude et la conception de matériels salutaires (ou salwares). En particulier, l'un des objectifs de ce projet est de combiner astucieusement plusieurs mécanismes de protection participant à la lutte contre la contrefaçon et le vol de circuits intégrés, pour construire un système d'activation complet. L'activation des circuits intégrés après leur fabrication permet de redonner leur contrôle au véritable propriétaire de la propriété intellectuelle. Dans ce manuscrit de thèse, nous proposons l'étude de trois mécanismes de protection participant à la lutte contre la contrefaçon et le vol de circuits intégrés. Dans un premier temps, nous étudierons l'insertion et la détection de watermarks dans les machines à états finies des systèmes numériques synchrones. Ce mécanisme de protection permet de détecter un vol ou une contrefaçon. Ensuite, une fonction physique non-clonable basée sur des oscillateurs en anneaux dont les oscillations sont temporaires est implantée et caractérisée sur FPGA. Ce mécanisme de protection permet d'identifier un circuit grâce à un identifiant unique créé grâce aux variations du processus de fabrication des circuits intégrés. Enfin, nous aborderons l'implantation matérielle d'algorithmes légers de chiffrement par bloc, qui permettent d'établir une communication sécurisée au moment de l'activation d'un circuit intégré
Hardware Acceleration for Homomorphic Encryption by Joël Cathebras( )

1 edition published in 2018 in English and held by 1 WorldCat member library worldwide

In this thesis, we propose to contribute to the definition of encrypted-computing systems for the secure handling of private data. The particular objective of this work is to improve the performance of homomorphic encryption. The main problem lies in the definition of an acceleration approach that remains adaptable to the different application cases of these encryptions, and which is therefore consistent with the wide variety of parameters. It is for that objective that this thesis presents the exploration of a hybrid computing architecture for accelerating Fan and Vercauteren's encryption scheme (FV).This proposal is the result of an analysis of the memory and computational complexity of crypto-calculation with FV. Some of the contributions make the adequacy of a non-positional number representation system (RNS) with polynomial multiplication Fourier transform over finite-fields (NTT) more effective. RNS-specific operations, inherently embedding parallelism, are accelerated on a SIMD computing unit such as GPU. NTT-based polynomial multiplications are implemented on dedicated hardware such as FPGA. Specific contributions support this proposal by reducing the storage and the communication costs for handling the NTTs' twiddle factors.This thesis opens up perspectives for the definition of micro-servers for the manipulation of private data based on homomorphic encryption
Arithmetic recodings for ECC cryptoprocessors with protections against side-channel attacks by Thomas Chabrier( )

1 edition published in 2013 in English and held by 1 WorldCat member library worldwide

This PhD thesis focuses on the study, the hardware design, the theoretical and practical validation, and eventually the comparison of different arithmetic operators for cryptosystems based on elliptic curves (ECC). Provided solutions must be robust against some side-channel attacks, and efficient at a hardware level (execution speed and area). In the case of ECC, we want to protect the secret key, a large integer, used in the scalar multiplication. Our protection methods use representations of numbers, and behaviour of algorithms to make more difficult some attacks. For instance, we randomly change some representations of manipulated numbers while ensuring that computed values are correct. Redundant representations like signed-digit representation, the double- (DBNS) and multi-base number system (MBNS) have been studied. A proposed method provides an on-the-fly MBNS recoding which operates in parallel to curve-level operations and at very high speed. All recoding techniques have been theoretically validated, simulated extensively in software, and finally implemented in hardware (FPGA and ASIC). A side-channel attack called template attack is also carried out to evaluate the robustness of a cryptosystem using a redundant number representation. Eventually, a study is conducted at the hardware level to provide an ECC cryptosystem with a regular behaviour of computed operations during the scalar multiplication so as to protect against some side-channel attacks
Cybersécurite matérielle et conception de composants dédiés au calcul homomorphe by Vincent Migliore( )

1 edition published in 2017 in French and held by 1 WorldCat member library worldwide

The emergence of internet and the improvement of communica- tion infrastructures have considerably increased the information flow around the world. This development has come with the emergence of new needs and new expectations from consumers. Communicate with family or colleagues, store documents or multimedia files, using innovative services which processes our personal data, all of this im- plies sharing with third parties some potentially sensitive data. If third parties are untrusted, they can manipulate without our agreement data we share with them. In this context, homomorphic encryption can be a good solution. Ho- momorphic encryption can hide to the third parties the data they are processing. However, at this point, homomorphic encryption is still complex. To process a few bits of clear data (cleartext), one needs to manage a few million bits of encrypted data (ciphertext). Thus, a computation which is usually simple becomes very costly in terms of computation time. In this work, we have improved the practicability of homomorphic en- cryption by implementing a specific accelerator. We have followed a software/hardware co-design approach with the help of Karatsuba algorithm. In particular, our approach is compatible with batching, a technique that “packs" several messages into one ciphertext. Our work demonstrates that the batching can be implemented at no important additional cost compared to non-batching approaches, and allows both reducing computation time (operations are processed in parallel) and the ciphertext/cleartext ratio
Contribution de l'arithmétique des ordinateurs aux implémentations résistantes aux attaques par canaux auxiliaires by Fangan Yssouf Dosso( )

1 edition published in 2020 in French and held by 1 WorldCat member library worldwide

This thesis focuses on two currently unavoidable elements of public key cryptography, namely modular arithmetic over large integers and elliptic curve scalar multiplication (ECSM). For the first one, we are interested in the Adapted Modular Number System (AMNS), which was introduced by Bajard et al. in 2004. In this system of representation, the elements are polynomials. We show that this system allows to perform modular arithmetic efficiently. We also explain how AMNS can be used to randomize modular arithmetic, in order to protect cryptographic protocols implementations against some side channel attacks. For the ECSM, we discuss the use of Euclidean Addition Chains (EAC) in order to take advantage of the efficient point addition formula proposed by Meloni in 2007. The goal is to first generalize to any base point the use of EAC for ECSM; this is achieved through curves with one efficient endomorphism. Secondly, we propose an algorithm for scalar multiplication using EAC, which allows error detection that would be done by an attacker we detail
Implantation sécurisée de protocoles cryptographiques basés sur les codes correcteurs d'erreurs by Tania Richmond( )

1 edition published in 2016 in French and held by 1 WorldCat member library worldwide

The first cryptographic protocol based on error-correcting codes was proposed in 1978 by Robert McEliece. Cryptography based on codes is called post-quantum because until now, no algorithm able to attack this kind of protocols in polynomial time, even using a quantum computer, has been proposed. This is in contrast with protocols based on number theory problems like factorization of large numbers, for which efficient Shor's algorithm can be used on quantum computers. Nevertheless, the McEliece cryptosystem security is based not only on mathematical problems. Implementation (in software or hardware) is also very important for its security. Study of side-channel attacks against the McEliece cryptosystem have begun in 2008. Improvements can still be done. In this thesis, we propose new attacks against decryption in the McEliece cryptosystem, used with classical Goppa codes, including corresponding countermeasures. Proposed attacks are based on evaluation of execution time of the algorithm or its power consumption analysis. Associate countermeasures are based on mathematical and algorithmic properties of the underlying algorithm. We show that it is necessary to secure the decryption algorithm by considering it as a whole and not only step by step
Accélérateurs matériels RNS flexibles pour la cryptographie asymétrique à haute sécurité by Libey Djath( )

1 edition published in 2021 in English and held by 1 WorldCat member library worldwide

Les implantations RNS de cryptosystèmes asymétriques actuels utilisent des ressources matérielles correspondant à la taille des opérandes traitées. Dans cette thèse, nous proposons une nouvelle approche dans l'implantation RNS de cryptosystèmes asymétriques qui permet une utilisation flexible de ressources matérielles. Dans un premier temps, un nouvel algorithme d'extension de base est présenté. Les extensions de bases sont, de par leurs coûts, des opérations critiques dans les implantations RNS. Notre nouvel algorithme d'extension de base utilise une approche hiérarchique dans le calcul du théorème chinois des restes. Comparé à l'algorithme d'extension de base de l'état de l'art, il présente un coût théorique réduit, qui se traduit par un gain en surface et en temps dans nos implantations HLS sur FPGA. Ensuite, nous implantons les deux algorithmes d'extension de base à partir de la nouvelle approche d'implantation RNS. Enfin, des multiplications scalaires utilisant chacune des deux extensions de base sont implantées avec la nouvelle approche. Nos implantations HLS sur FPGA utilisent des ressources matérielles en quantité flexible. De plus, quoique comparables en compromis surface/temps à ceux de l'état de l'art, la plupart de nos résultats sont bien plus petits
Durabilité de l'acier inoxydable martensitique 17-4 PH obtenu par fabrication additive by Maxime Montoya( )

1 edition published in 2019 in French and held by 1 WorldCat member library worldwide

The goal of this work is to propose new methods that provide both a high security and a high energy efficiency for integrated circuits for the IoT.On the one side, we study the security of a mechanism dedicated to energy management. Wake-up radios trigger the wake-up of integrated circuits upon receipt of specific wake-up tokens, but they are vulnerable to denial-of-sleep attacks, during which an attacker replays such a token indefinitely to wake-up a circuit and deplete its battery. We propose a new method to generate unpredictable wake-up tokens at each wake-up, which efficiently prevents these attacks at the cost of a negligible energy overhead.On the other side, we improve on the energy efficiency of hardware countermeasures against fault and side-channel attacks, with two different approaches. First, we present a new combined countermeasure, which increases by four times the power consumption compared to an unprotected implementation, introduces no performance overhead, and requires less than 8 bits of randomness. Therefore, it has a lower energy overhead than existing combined protections. It consists in an algorithm-level power balancing that inherently detects faults. Then, we propose an adaptive implementation of hardware countermeasures, which consists in applying or removing these countermeasures on demand, during the execution of the protected algorithm, in order to tune the security level and the energy consumption. A security evaluation of all the proposed countermeasures indicates that they provide an efficient protection against existing hardware attacks
Contribution à l'arithmétique des ordinateurs et applications aux systèmes embarqués by Nicolas Brunie( )

1 edition published in 2014 in English and held by 1 WorldCat member library worldwide

In the last decades embedded systems have been challenged with more and more application variety, each time more constrained. This implies an ever growing need for performances and energy efficiency in arithmetic units. This work studies solutions ranging from hardware to software to improve arithmetic support in embedded systems. Some of these solutions were integrated in Kalray's MPPA processor. The first part of this work focuses on floating-Point arithmetic support in the MPPA. It starts with the design of a floating-Point unit (FPU) based on the classical FMA (Fused Multiply-Add) operator. The improvements we suggest, implement and evaluate include a mixed precision FMA, a 3-Operand add and a 2D scalar product, each time with a single rounding and support for subnormal numbers. It then considers the implementation of division and square root. The FPU is reused and modified to optimize the software implementations of those primitives at a lower cost. Finally, this first part opens up on the development of a code generator designed for the implementation of highly optimized mathematical libraries in different contexts (architecture, accuracy, latency, throughput). The second part studies a reconfigurable coprocessor, a hardware operator that could be dynamically modified to adapt on the fly to various applicative needs. It intends to provide performance close to ASIC implementation, with some of the flexibility of software. One of the addressed challenges is the integration of such a reconfigurable coprocessor into the low power embedded cluster of the MPPA. Another is the development of a software framework targeting the coprocessor and allowing design space exploration. The last part of this work leaves micro-Architecture considerations to study the efficient use of parallel arithmetic resources. It presents an improvement of regular architectures (Single Instruction Multiple Data), like those found in graphic processing units (GPU), for the execution of divergent control flow graphs
Contrer l'attaque Simple Power Analysis efficacement dans les applications de la cryptographie asymétrique, algorithmes et implantations by Jean-Marc Robert( )

1 edition published in 2015 in French and held by 1 WorldCat member library worldwide

The development of online communications and the Internet have made encrypted data exchange fast growing. This has been possible with the development of asymmetric cryptographic protocols, which make use of arithmetic computations such as modular exponentiation of large integer or elliptic curve scalar multiplication. These computations are performed by various platforms, including smart-cards as well as large and powerful servers. The platforms are subject to attacks taking advantage of information leaked through side channels, such as instantaneous power consumption or electromagnetic radiations.In this thesis, we improve the performance of cryptographic computations resistant to Simple Power Analysis. On modular exponentiation, we propose to use multiple multiplications sharing a common operand to achieve this goal. On elliptic curve scalar multiplication, we suggest three different improvements : over binary fields, we make use of improved combined operation AB,AC and AB+CD applied to Double-and-add, Halve-and-add and Double/halve-and-add approaches, and to the Montgomery ladder ; over binary field, we propose a parallel Montgomery ladder ; we make an implementation of a parallel approach based on the Right-to-left Double-and-add algorithm over binary and prime fields, and extend this implementation to the Halve-and-add and Double/halve-and-add over binary fields
 
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French (14)

English (9)