WorldCat Identities

Sirdey, Renaud

Overview
Works: 20 works in 22 publications in 2 languages and 29 library holdings
Genres: Academic theses 
Roles: Other, Opponent, Thesis advisor, Author
Publication Timeline
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Most widely held works by Renaud Sirdey
Stream Ciphers: A Practical Solution for Efficient Homomorphic-Ciphertext Compression by Anne Canteaut( )

2 editions published in 2018 in English and held by 4 WorldCat member libraries worldwide

Stochastic graph partitioning: quadratic versus SOCP formulations by Dang Phuong Nguyen( )

1 edition published in 2015 in English and held by 2 WorldCat member libraries worldwide

Systèmes de cryptocalculs, compilation et support d'exécution by Simon Fau( )

1 edition published in 2016 in English and held by 2 WorldCat member libraries worldwide

Our approach in this thesis was to identify where FHE could be used in computer science and to build an experimental platform that allow us to test real-life algorithm running on homomorphically-encrypted data. The first part of this thesis is dedicated to the state of the art. We first present homomorphic encryption schemes designed before 2008 and then move to the Fully Homomorphic Encryption period. We describe several schemes of interest for this thesis and discuss FHE implementations. Finally, we present Yao's garbled circuits as they can solve similar problems as FHE and briefly talk about Functional Encryption (FE). The second part of this thesis is for our contributions to the subject. We begin by explaining how FHE can be useful in various scenarios and try to provide practical use cases that we identified during the thesis. Then, we describe our approach to perform computations on encrypted data using FHE and explain how we were able to build on just the homomorphic addition and multiplication a platform for the execution in the encrypted domain of a wide range of algorithms. We then detail our solution for performing private queries on an encrypted database using homomorphic encryption. In a final chapter, we present our experimental results
Data flow oriented hardware design of RNS-based polynomial multiplication for SHE acceleration by Joël Cathébras( )

1 edition published in 2018 in English and held by 2 WorldCat member libraries worldwide

The robust binomial approach to chance-constrained optimization problems with application to stochastic partitioning of large process networks by Oana Stan( )

1 edition published in 2014 in English and held by 2 WorldCat member libraries worldwide

Modèles et algorithmes pour la reconfiguration de systèmes répartis utilisés en téléphonie cellulaire by Renaud Sirdey( Book )

2 editions published in 2007 in French and held by 2 WorldCat member libraries worldwide

This PhD thesis is devoted to the study of a strongly N P-hard resource-constrained scheduling problem: the Process Move Programming problem. This problem arises from the telecommunication industry, in relation to the operability of certain high availability real-time distributed systems such as the BSCe3, a wireless switching system commercialized by Nortel. Informally, the problem consists, starting from an arbitrary admissible initial distribution of pro cesses on the processors of a distributed system, in finding a least disruptive sequence of operations (non-impacting process migrations or temporary process interruptions) at the end of which the system ends up in another predefined arbitrary state. The main constraint lies in the fact that the capacity of the processors must not be exceeded during the reconfiguration. We have approached this scheduling problem from different angles. First, we have established its strong N P-hardness and exhibited a number of polynomial special cases. Then, in terms of exact resolution in the general case, we have devised two tree search algorithms: one of them is based on the investigation of the combinatorial structure of the problem and the other on polyhedral insights. The practical relevance of these algorithms has been demonstrated through extensive computational experiments. Lastly, motivated by the constraints implied by the real-time nature of our industrial application, we have designed a simulated annealing-based efficient approximate resolution algorithm and, building on our work on exact resolution, empirically demonstrated its practical ability to produce acceptable solutions, in a precisely defined sense
Implantation matérielle de chiffrements homomorphiques by Asma Mkhinini( )

1 edition published in 2017 in French and held by 2 WorldCat member libraries worldwide

Une des avancées les plus notables de ces dernières années en cryptographie est sans contredit l'introduction du premier schéma de chiffrement complètement homomorphe par Craig Gentry. Ce type de système permet de réaliser des calculs arbitraires sur des données chiffrées, sans les déchiffrer. Cette particularité permet de répondre aux exigences de sécurité et de protection des données, par exemple dans le cadre en plein développement de l'informatique en nuage et de l'internet des objets. Les algorithmes mis en œuvre sont actuellement très coûteux en temps de calcul, et généralement implantés sous forme logicielle. Les travaux de cette thèse portent sur l'accélération matérielle de schémas de chiffrement homomorphes. Une étude des primitives utilisées par ces schémas et la possibilité de leur implantation matérielle est présentée. Ensuite, une nouvelle approche permettant l'implantation des deux fonctions les plus coûteuses est proposée. Notre approche exploite les capacités offertes par la synthèse de haut niveau. Elle a la particularité d'être très flexible et générique et permet de traiter des opérandes de tailles arbitraires très grandes. Cette particularité lui permet de viser un large domaine d'applications et lui autorise d'appliquer des optimisations telles que le batching. Les performances de notre architecture de type co-conception ont été évaluées sur l'un des cryptosystèmes homomorphes les plus récents et les plus efficaces. Notre approche peut être adaptée aux autres schémas homomorphes ou plus généralement dans le cadre de la cryptographie à base de réseaux
Hardware Acceleration for Homomorphic Encryption by Joël Cathebras( )

1 edition published in 2018 in English and held by 1 WorldCat member library worldwide

In this thesis, we propose to contribute to the definition of encrypted-computing systems for the secure handling of private data. The particular objective of this work is to improve the performance of homomorphic encryption. The main problem lies in the definition of an acceleration approach that remains adaptable to the different application cases of these encryptions, and which is therefore consistent with the wide variety of parameters. It is for that objective that this thesis presents the exploration of a hybrid computing architecture for accelerating Fan and Vercauteren's encryption scheme (FV).This proposal is the result of an analysis of the memory and computational complexity of crypto-calculation with FV. Some of the contributions make the adequacy of a non-positional number representation system (RNS) with polynomial multiplication Fourier transform over finite-fields (NTT) more effective. RNS-specific operations, inherently embedding parallelism, are accelerated on a SIMD computing unit such as GPU. NTT-based polynomial multiplications are implemented on dedicated hardware such as FPGA. Specific contributions support this proposal by reducing the storage and the communication costs for handling the NTTs' twiddle factors.This thesis opens up perspectives for the definition of micro-servers for the manipulation of private data based on homomorphic encryption
Functional encryption applied to privacy-preserving classification : practical use, performances and security by Damien Ligier( )

1 edition published in 2018 in English and held by 1 WorldCat member library worldwide

Machine Learning (ML) algorithms have proven themselves very powerful. Especially classification, enabling to efficiently identify information in large datasets. However, it raises concerns about the privacy of this data. Therefore, it brought to the forefront the challenge of designing machine learning algorithms able to preserve confidentiality.This thesis proposes a way to combine some cryptographic systems with classification algorithms to achieve privacy preserving classifier. The cryptographic system family in question is the functional encryption one. It is a generalization of the traditional public key encryption in which decryption keys are associated with a function. We did some experimentations on that combination on realistic scenario using the MNIST dataset of handwritten digit images. Our system is able in this use case to know which digit is written in an encrypted digit image. We also study its security in this real life scenario. It raises concerns about uses of functional encryption schemes in general and not just in our use case. We then introduce a way to balance in our construction efficiency of the classification and the risks
Cryptographie légère intrinsèquement résistante aux attaques physiques pour l'Internet des objets. by Benjamin Lac( )

1 edition published in 2018 in French and held by 1 WorldCat member library worldwide

The Internet of Things has many application areas and offers huge potentials for businesses, industries and users. Our study deals with the cryptographic requirements and the security issues of connected objects, which specificities are the large number of data they handle every day, and the fact they are often fielded in hostile environment, physically accessible to any type of potential attacker.Side-channel attacks and fault attacks are the two main categories of physical attacks. In our research works, we analyze these different techniques of physical attacks and the existing countermeasures to thwart them, and we introduce two new attack paths that we have experimentally validated in laboratory on a recent family of symmetric encryption schemes: the interleaving structures.In order to meet the security needs and the high performance constraints of the connected objects, we propose a new generic software countermeasure based on redundancy to thwart most of the physical attacks that we called the IRC. We then study the deployment of the IRC on the existing encryption schemes, and its resistance to physical attacks.Finally, we introduce GARFIELD: a new lightweight block cipher adapted to the IRC in order to ensure a good compromise between security and performance. We check its resistance to conventional mathematical attacks and we propose several implementations with different security levels, for the applications of the Internet of Things, for which we analyze the resulting performances and the validity in practice
Contributions à l'optimisation combinatoire pour l'embarqué : des autocommutateurs cellulaires aux microprocesseurs massivement parallèles by Renaud Sirdey( Book )

1 edition published in 2012 in French and held by 1 WorldCat member library worldwide

Image fusion using wavelets by Renaud Sirdey( )

1 edition published in 1998 in English and held by 1 WorldCat member library worldwide

PAnTHErS : un outil d'aide pour l'analyse et l'exploration d'algorithmes de chiffrement homomorphe by Cyrielle Feron( )

1 edition published in 2018 in French and held by 1 WorldCat member library worldwide

Homomorphic encryption (HE) is a cryptographic system allowing to manipulate encrypted data. This property enables a user to delegate treatments on private data to an untrusted third person on a distant server, without loss of confidentiality.Even if current researches in HE domain are still young, numerous HE schemes have been created. Nevertheless, those schemes suffer from some drawbacks, especially, from too long execution times and important memory costs. These restrictions make difficult to compare schemes in order to define which one is the most appropriate for a given application, i. e. the less expensive in terms of time and memory.This thesis presents PAnTHErS, a tool gathering several features to answer to the previous problem. In the tool PAnTHErS, homomorphic encryption schemes are first represented into a common structure thanks to a modeling method. Then, a theoretical analysis evaluates, in the worst case, computational complexity and memory consumption of those schemes according to given input parameters. Finally, a calibration phase enables conversion of theoretical analysis into concrete results: computational complexity is converted into an estimated execution time in seconds and memory cost into an estimated consumption in mebibytes.These gathered features allowed the creation of an exploration method which, from an application, selects best schemes and associated input parameters that implies close to optimal execution times and memory costs
Evaluation de l'affectation des tâches sur une architecture à mémoire distribuée pour des modèles flot de données by Youen Lesparre( )

1 edition published in 2017 in English and held by 1 WorldCat member library worldwide

With the increasing use of smart-phones, connected objects or automated vehicles, embedded systems have become ubiquitous in our living environment. These systems are often highly constrained in terms of power consumption and size. They are more and more implemented with many-core processor array that allow, rapid design to meet stringent real-time constraints while operating at relatively low frequency, with reduced power consumption.Running an application on a processor array requires dispatching its tasks on the processors in order to meet capacity and performance constraints. This mapping problem is known to be NP-complete.The contributions of this thesis are threefold:First we extend important notions from the Cyclo-Static Dataflow Graph to the Phased Computation Graph model and two equivalent sufficient conditions of liveness.Second, we present a random dataflow graph generator able to generate Synchonous Dataflow Graphs, Cyclo-Static Dataflow Graphs and Phased Computation Graphs. The Generator, is able to generate live dataflow of up to 10,000 tasks in less than 30 seconds. It is compared with SDF3 and PREESM.Third and most important, we propose a new method of evaluation of a mapping using the Synchonous Dataflow Graph and the Cyclo-Static Dataflow Graph models. The method evaluates efficiently the memory footprint of the communications of a dataflow graph mapped on a distributed architecture. The evaluation is declined in two versions, the first guarantees a live mapping while the second accounts for a constraint on throughput.The evaluation method is experimented on dataflow graphs from Turbine and on real-life applications
Exploration of parallel graph-processing algorithms on distributed architectures by Julien Collet( )

1 edition published in 2017 in English and held by 1 WorldCat member library worldwide

With the advent of ever-increasing graph datasets in a large number of domains, parallel graph-processing applications deployed on distributed architectures are more and more needed to cope with the growing demand for memory and compute resources. Though large-scale distributed architectures are available, notably in the High-Performance Computing (HPC) domain, the programming and deployment complexity of such graphprocessing algorithms, whose parallelization and complexity are highly data-dependent, hamper usability. Moreover, the difficult evaluation of performance behaviors of these applications complexifies the assessment of the relevance of the used architecture. With this in mind, this thesis work deals with the exploration of graph-processing algorithms on distributed architectures, notably using GraphLab, a state of the art graphprocessing framework. Two use-cases are considered. For each, a parallel implementation is proposed and deployed on several distributed architectures of varying scales. This study highlights operating ranges, which can eventually be leveraged to appropriately select a relevant operating point with respect to the datasets processed and used cluster nodes. Further study enables a performance comparison of commodity cluster architectures and higher-end compute servers using the two use-cases previously developed. This study highlights the particular relevance of using clustered commodity workstations, which are considerably cheaper and simpler with respect to node architecture, over higher-end systems in this applicative context. Then, this thesis work explores how performance studies are helpful in cluster design for graph-processing. In particular, studying throughput performances of a graph-processing system gives fruitful insights for further node architecture improvements. Moreover, this work shows that a more in-depth performance analysis can lead to guidelines for the appropriate sizing of a cluster for a given workload, paving the way toward resource allocation for graph-processing. Finally, hardware improvements for next generations of graph-processing servers areproposed and evaluated. A flash-based victim-swap mechanism is proposed for the mitigation of unwanted overloaded operations. Then, the relevance of ARM-based microservers for graph-processing is investigated with a port of GraphLab on a NVIDIA TX2-based architecture
A journey towards practical fully homomorphic encryption by Guillaume Bonnoron( )

1 edition published in 2018 in English and held by 1 WorldCat member library worldwide

Craig Gentry a proposé en 2009 le premier schéma de chiffrement complétement homomorphe. Depuis, un effort conséquent a été, et est toujours, fourni par la communauté scientifique pour rendre utilisable ce nouveau type de cryptographie. Son côté révolutionnaire tient au fait qu'il permet d'effectuer des traitements directement sur des données chiffrées (sans que l'entité réalisant les traitements ait besoin de les déchiffrer). Plusieurs pistes se sont développées en parallèle, explorant d'un côté des schémas complétement homomorphes, plus flexibles entermes d'applications mais plus contraignants en termes de taille de données ou en coût de calcul, et de l'autre côté des schémas quelque peu homomorphes, moins flexibles mais aussi moins coûteux. Cette thèse, réalisée au sein de la chaire de cyberdéfense des systèmes navals, s'inscrit dans cette dynamique. Nous avons endossé divers rôles. Tout d'abord un rôle d'attaquant pour éprouver la sécurité des hypothèses sous-jacentes aux propositions. Ensuite, nous avons effectué un état de l'art comparatif des schémas quelque peu homomorphes les plus prometteurs afin d'identifier le(s) meilleur(s) selon les cas d'usages, et de donner des conseils dans le choix des paramètres influant sur leur niveau de sécurité, la taille des données chiffrées et le coût algorithmique des calculs. Enfin, nous avons endossé le rôle du concepteur en proposant un nouveau schéma complétement homomorphe performant, ainsi que son implémentation mise à disposition sur github
Placement de graphes de tâches de grande taille sur architectures massivement multicoeurs by Karl-Eduard Berger( )

1 edition published in 2015 in English and held by 1 WorldCat member library worldwide

This Ph.D thesis is devoted to the study of the mapping problem related to massively parallel embedded architectures. This problem arises from industrial needs like energy savings, performance demands for synchronous dataflow applications. This problem has to be solved considering three criteria: heuristics should be able to deal with applications with various sizes, they must meet the constraints of capacities of processors and they have to take into account the target architecture topologies. In this thesis, tasks are organized in communication networks, modeled as graphs. In order to determine a way of evaluating the efficiency of the developed heuristics, mappings, obtained by the heuristics, are compared to a random mapping. This comparison is used as an evaluation metric throughout this thesis. The existence of this metric is motivated by the fact that no comparative heuristics can be found in the literature at the time of writing of this thesis. In order to address this problem, two heuristics are proposed. They are able to solve a dataflow process network mapping problem, where a network of communicating tasks is placed into a set of processors with limited resource capacities, while minimizing the overall communication bandwidth between processors. They are applied on task graphs where weights of tasks and edges are unitary set. The first heuristic, denoted as Task-wise Placement, places tasks one after another using a notion of task affinities. The second algorithm, named Subgraph-wise Placement, gathers tasks in small groups then place the different groups on processors using a notion of affinities between groups and processors. These algorithms are tested on tasks graphs with grid or logic gates network topologies. Obtained results are then compared to an algorithm present in the literature. This algorithm maps task graphs with moderated size on massively parallel architectures. In addition, the random based mapping metric is used in order to evaluate results of both heuristics. Then, in a will to address problems that can be found in industrial cases, application cases are widen to tasks graphs with tasks and edges weights values similar to those that can be found in the industry. A progressive construction heuristic named Regret Based Approach, based on game theory, is proposed. This heuristic maps tasks one after another. The costs of mapping tasks according to already mapped tasks are computed. The process of task selection is based on a notion of regret, present in game theory. The task with the highest value of regret for not placing it, is pointed out and is placed in priority. In order to check the strength of the algorithm, many types of task graphs (grids, logic gates networks, series-parallel, random, sparse matrices) with various size are generated. Tasks and edges weights are randomly chosen using a bimodal law parameterized in order to have similar values than industrial applications. Obtained results are compared to the Task Wise placement, especially adapted for non-unitary values. Moreover, results are evaluated using the metric defined above
Contributions à des problèmes de partitionnement de graphe sous contraintes de ressources by Dang Phuong Nguyen( )

1 edition published in 2016 in English and held by 1 WorldCat member library worldwide

The graph partitioning problem is a fundamental problem in combinatorial optimization. The problem refers to partitioning the set of nodes of an edge weighted graph in several disjoint node subsets (or clusters), so that the sum of the weights of the edges whose end-nodes are in different clusters is minimized. In this thesis, we study the graph partitioning problem on graph with (non negative) node weights with additional set constraints on the clusters (GPP-SC) specifying that the total capacity (e.g. the total node weight, the total capacity over the edges having at least one end-node in the cluster) of each cluster should not exceed a specified limit (called capacity limit). This differs from the variants of graph partitioning problem most commonly addressed in the literature in that:-The number of clusters is not imposed (and is part of the solution),-The weights of the nodes are not homogeneous.The subject of the present work is motivated by the task allocation problem in multicore structures. The goal is to find a feasible placement of all tasks to processors while respecting their computing capacity and minimizing the total volume of interprocessor communication. This problem can be formulated as a graph partitioning problem under knapsack constraints (GPKC) on sparse graphs, a special case of GPP-SC. Moreover, in such applications, the case of uncertain node weights (weights correspond for example to task durations) has to be taken into account.The first contribution of the present work is to take into account the sparsity character of the graph G = (V,E). Most existing mathematical programming models for the graph partitioning problem use O(|V|^3) metric constraints to model the partition of nodes and thus implicitly assume that G is a complete graph. Using these metric constraints in the case where G is not complete requires adding edges and constraints which may greatly increase the size of the program. Our result shows that for the case where G is a sparse graph, we can reduce the number of metric constraints to O(|V||E|).The second contribution of present work is to compute lower bounds for large size graphs. We propose a new programming model for the graph partitioning problem that make use of only O(m) variables. The model contains cycle inequalities and all inequalities related to the paths in the graph to formulate the feasible partitions. Since there are an exponential number of constraints, solving the model needs a separation method to speed up the computation times. We propose such a separation method that use an all pair shortest path algorithm thus is polynomial time. Computational results show that our new model and method can give tight lower bounds for large size graphs of thousands of nodes
Memory Study and Dataflow Representations for Rapid Prototyping of Signal Processing Applications on MPSoCs by Karol Desnos( )

1 edition published in 2014 in English and held by 1 WorldCat member library worldwide

The development of embedded Digital Signal Processing (DSP) applications for Multiprocessor Systems-on-Chips (MPSoCs) is a complex task requiring the consideration of many constraints including real-time requirements, power consumption restrictions, and limited hardware resources. To satisfy these constraints, it is critical to understand the general characteristics of a given application: its behavior and its requirements in terms of MPSoC resources. In particular, the memory requirements of an application strongly impact the quality and performance of an embedded system, as the silicon area occupied by the memory can be as large as 80% of a chip and may be responsible for a major part of its power consumption. Despite the large overhead, limited memory resources remain an important constraint that considerably increases the development time of embedded systems. Dataflow Models of Computation (MoCs) are widely used for the specification, analysis, and optimization of DSP applications. The popularity of dataflow MoCs is due to their great analyzability and their natural expressivity of the parallelism of a DSP application. The abstraction of time in dataflow MoCs is particularly suitable for exploiting the parallelism offered by heterogeneous MPSoCs. In this thesis, we propose a complete method to study the important aspect of memory characteristic of a DSP application modeled with a dataflow graph. The proposed method spans the theoretical, architecture-independent memory characterization to the quasi-optimal static memory allocation of an application on a real shared-memory MPSoC. The proposed method, implemented as part of a rapid prototyping framework, is extensively tested on a set of state-of-the-art applications from the computer-vision, the telecommunication, and the multimedia domains. Then, because the dataflow MoC used in our method is unable to model applications with a dynamic behavior, we introduce a new dataflow meta-model to address the important challenge of managing dynamics in DSP-oriented representations. The new reconfigurable and composable dataflow meta-model strengthens the predictability, the conciseness and the readability of application descriptions
Cybersécurite matérielle et conception de composants dédiés au calcul homomorphe by Vincent Migliore( )

1 edition published in 2017 in French and held by 1 WorldCat member library worldwide

The emergence of internet and the improvement of communica- tion infrastructures have considerably increased the information flow around the world. This development has come with the emergence of new needs and new expectations from consumers. Communicate with family or colleagues, store documents or multimedia files, using innovative services which processes our personal data, all of this im- plies sharing with third parties some potentially sensitive data. If third parties are untrusted, they can manipulate without our agreement data we share with them. In this context, homomorphic encryption can be a good solution. Ho- momorphic encryption can hide to the third parties the data they are processing. However, at this point, homomorphic encryption is still complex. To process a few bits of clear data (cleartext), one needs to manage a few million bits of encrypted data (ciphertext). Thus, a computation which is usually simple becomes very costly in terms of computation time. In this work, we have improved the practicability of homomorphic en- cryption by implementing a specific accelerator. We have followed a software/hardware co-design approach with the help of Karatsuba algorithm. In particular, our approach is compatible with batching, a technique that “packs" several messages into one ciphertext. Our work demonstrates that the batching can be implemented at no important additional cost compared to non-batching approaches, and allows both reducing computation time (operations are processed in parallel) and the ciphertext/cleartext ratio
 
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English (15)

French (7)