WorldCat Identities

Lu, Guo Neng (1956-....).

Overview
Works: 23 works in 27 publications in 2 languages and 33 library holdings
Roles: Other, Thesis advisor, Opponent, Author
Publication Timeline
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Most widely held works by Guo Neng Lu
Étude et conception d'opérateurs analogiques en CMOS, pour des applications basses fréquences, faibles tensions et faibles consommations by Aimad El Mourabit( Book )

2 editions published in 2005 in French and held by 2 WorldCat member libraries worldwide

Le travail présenté dans cette thèse contribue au développement d'opérateurs analogiques faible tension et faible consommation en CMOS pour le traitement du signal sur puce. Il s'inscrit dans le cadre du développement de systèmes miniaturisés de microanalyse pour applications biomédicales. Un opérateur étudié est un OTA (Amplificateur Opérationnel de Transconductance) de faible transconductance Gm. C'est un bloc clé pour concevoir des filtres Gm-C monolithique très basses fréquences. On peut montrer que l'OTA à base de transistors MOS à entrées multiples et grilles flottantes (MIFG-MOS) fonctionnant en faible inversion permet à la fois l'obtention de faible Gm et l'extension de la zone linéaire. La linéarité peut encore être améliorée jusqu'aux limites de la tension d'alimentation par l'implémentation d'une technique de suppression du terme de distorsion cubique. On propose ainsi des structures d'OTA sous 1,5V avec une consommation inférieure à 1µW pour des filtres Gm-C à très faibles fréquences de coupures. D'autres opérateurs, comme par exemple le multiplieur, sont aussi étudiés. Là encore, en utilisant des transistors MIFG-MOS et en appliquant la technique d'annulation du terme de distorsion cubique, plusieurs structures d'opérateurs faibles tensions mais avec une grande plage dynamique sont développées
Développement d'une photodiode à stockage de charges vertical pour les capteurs d'image CMOS éclairés par la face arrière by Julien Michelot( )

1 edition published in 2012 in French and held by 2 WorldCat member libraries worldwide

Etude des bruits basse fréquence dans les détecteurs infrarouge quantiques refroidis à base de HgCdTe by Alexandre Brunner( )

1 edition published in 2015 in French and held by 2 WorldCat member libraries worldwide

Les exigences liées aux photodétecteurs modernes font de la maîtrise du niveau de bruit un enjeu majeur pour les technologies de demain. Le Random Telegraph Signal (RTS), à l'origine de « pixels clignotants » en imagerie, gênants pour l'utilisateur comme pour les algorithmes de traitement et d'analyse du signal, fait partie des sources de bruit problématiques. Ce travail en fait l'étude dans les détecteurs infrarouge quantiques refroidis à base de HgCdTe. Le premier chapitre présentera des généralités sur la détection infrarouge, le fonctionnement des photodétecteurs quantiques, le matériau HgCdTe, et le bruit. On exposera ensuite les études réalisées sur le bruit RTS dans les imageurs pour différents domaines de l'infrarouge et trois technologies de fabrication de photodiodes. L'évolution des caractéristiques du bruit (amplitude et fréquence) en fonction de la température du détecteur, du flux de photons reçus, de la polarisation appliquée, ou encore du temps d'intégration seront également analysées. Le troisième chapitre sera consacré à l'origine du bruit RTS. Pour cela, différentes architectures d'étages d'entrée de circuit de lecture et de technologies de fabrication de photodiodes seront passées en revue. Enfin, le dernier chapitre exposera l'étude par Deep Level Transient Spectroscopy des défauts profonds électriquement actifs dans la bande interdite du HgCdTe pour le proche infrarouge (Short Wave InfraRed, à 2,5µm)
Etude des bruits basse fréquence et des défauts électriquement actifs dans les détecteurs infrarouge refroidis by Pierre Guinedor( )

1 edition published in 2019 in French and held by 2 WorldCat member libraries worldwide

Modélisation de la barriere de Schottky : établissement et comportement sous polarisation by Guo Neng Lu( Book )

2 editions published in 1986 in French and held by 2 WorldCat member libraries worldwide

Une modélisation de l'interface métal-semiconducteur est établie en tenant compte d'états d'interface pénétrant dans le semiconducteur. La forme des bandes d'énergie et la hauteur de la barrière de Schottky sont obtenues et discutées en fonction de différents paramètres : distribution en énergie, densité, profondeur de pénétration des états ; dopage du semiconducteur ; nature du métal. Des règles dancrage du niveau de Fermi sont dégagées et confrontées à l'expérience sur les principaux semiconducteurs (Si, GaAs, InP). Le comportement de l'interface M-S sans polarisation électrique est ensuite décrit. La modification de la charge électrique interfaciale avec la tension appliquée est prise en compte pour expliquer les anomalies de conduction fréquemment rencontrées dans les dispositifs réels
Conception d'un convertisseur Analogique-numérique à rampe par morceaux pour capteur d'image avec techniques de calibration by Cédric Pastorelli( )

1 edition published in 2016 in French and held by 2 WorldCat member libraries worldwide

The aim of this thesis is the implementation of new image sensors for mobile in CMOS (Complementary Metal Oxide Semiconductor) technology to meet strong market demand. Next generations of products require image sensors with high performances.These improvements would change the image quality with low noise architecture in one hand, and the use of new technologies to increase the signal level, or reduce the power consumption in the other hand. The gain in image quality leads to increase the size of the pixel's array, and the resolution of the data -the conversion speed becoming critical-. The subject of this thesis focuses on improving this latter point. A comparative study has been made between several architectures to find the best solution that would fit our needs.The ramp converter is the most suitable for small pixels, but his main drawback is the conversion time that requires 2N clock cycles. To obtain a higher frame rate, a method taking advantage of the photon noise has been presented. This readout circuit is based on a piecewise linear ramp converter and an algorithm that allows the linearization of the data. Furthermore, for noise reduction, the new architecture must take into account the digital correlated double sampling. During the period of design, test modes have also been designed and implemented to allow characterization of the circuit.The innovative part is the use of a piecewise linear ramp, which in simulation, reduces the readout time of 1us per row. However, this element needs calibration. A CMOS image sensor prototype of 13Mpixel has been made in 65 nm, 5 levels of metals, and 1 level of poly standard CMOS technology. Measurements showed that the INL and DNL of the converter were as good as with a conventional linear ramp. A careful consideration has been given to the measurement of noise, which unfortunately is higher than a "conventional" sensor. However, the consumption remains the same while having a faster conversion speed. The solutions are simple to integrate structurally and easy to implement. They have the advantage of not affecting the surface of the pixel, thus preserve the performance of the latter. The results found from the silicon-on measures are very encouraging, we gain almost 20% of the conversion time
Étude, conception et test de micro capteurs RMN et de circuits électroniques associés en vue de réalisation de micro systèmes pour des applications biomédicales by Tewfik Cherifi( Book )

2 editions published in 2005 in French and held by 2 WorldCat member libraries worldwide

Développement d'un pixel photogate éclairé par la face arrière by Andrej Suler( )

1 edition published in 2019 in French and held by 2 WorldCat member libraries worldwide

Nowadays image sensors look neither to be efficient, but rather to be adapted to their environment or to new uses. Autonomous machines and vehicles can be mentioned for instance. Because of image quality and cost, a large majority of applications employs CMOS pixels and pinned back-side illuminated photodiodes.The originality of the solution proposed in this manuscript relies on the integration of a photogate, used by CCD sensors, inside a CMOS pixel. Its use optimize the available space inside the pixel and decrease the number of implantation needed to its realization. This development has also led to the use of specific transfer gate. Both structures have been created during this thesis and designed using simulation and specific test structures.The characterization of the developed pixel demonstrate many assets such as an increase of saturation charges and a reduction of dark current. Furthermore, a detailed study of the dark currant indicates a more gathered pixel distribution, allowing the identification of contaminants and a better temperature handling in comparison to a classical photodiode.The proposed structure offers many perspectives such as reduction of the pixel pitch or its potential use in an environment with a temperature constraint
Etude du Convertisseur Temps-Numérique de très haute précision pour des applications en Physique des particules pour les mises à jour du détecteur CMS auprès du LHC by Amina Annagrebah( )

1 edition published in 2021 in French and held by 1 WorldCat member library worldwide

The revival of the experiments at the LHC collider at CERN will call on increasingly efficient detectors in order to face the challenge of increase in the number of collisions. This increase will lead to more confusion of products from different collisions. Among the solutions that will reduce this confusion and improve the construction of physical processes, time-accurate labeling can being considered. Time-accurate measurement of the detection of particles produced in collisions will also achieve increased spatial precision in determining the point of interaction. Accurate time measurement is possible thanks to the use of Resistive Plate Chamber (RPC) type detectors developed by IP2I physicists and proposed to equip the CMS detector of the LHC. To achieve this, the reading electronics must be able to preserve the performance of these detectors by achieving excellent temporal resolution. In this thesis, we describe the development and demonstration of suitable architectures for the precise measurement of short time intervals. Our goal is to evaluate and demonstrate architectures that can be integrated with standard 130nm CMOS technology. Several architectures were analyzed, one of which, based on Vernier-type ring oscillators, was selected for a more detailed analysis. This led to the construction of a demonstration integrated circuit. In addition, a new high resolution multiphase architecture was proposed and the analysis performed confirmed good temporal resolution
Développement d'un pixel innovant de type "temps de vol" pour des capteurs d'images 3D-CMOS by Boris Rodrigues Gonçalves( )

1 edition published in 2018 in French and held by 1 WorldCat member library worldwide

Nouvelle architecture de pixel CMOS éclairé par la face arrière, intégrant une photodiode à collection de trous et une chaine de lecture PMOS pour capteurs d'image en environnement ionisant by Bastien Mamdy( )

1 edition published in 2016 in French and held by 1 WorldCat member library worldwide

Thanks to the growing smartphones and tablets consumer markets, CMOS image sensors have benefited from major technology developments and are able to rival with and even outperform CCD sensors. In parallel, for spatial and medical imaging applications, CMOS sensors have been developed using technologies recognized for their robustness in harsh ionizing environment. This Ph.D. thesis work aims at combining in one single pixel architecture the latest technology developments driven by consumer applications with a novel solution for radiation hardening recently developed at STMicroelectronics. For the first time, this innovative back-side illuminated pixel architecture integrates within a 1.4µm pitch a vertical pinned photodiode based on hole-collection, a PMOS readout chain and deep trench isolation with either passive or active interface passivation. This pixel has been developed using 3D-TCAD simulations allowing fast and efficient optimization of its fabrication process. Through a series of electro-optical characterizations, we have compared its performances to its N-type equivalent before and after irradiation with gamma rays. The pixel developed during this thesis exhibits intrinsically lower level of dark current than its N-type counterpart and improved radiation hardness. Active passivation of deep trench isolation greatly decreases the impact of degradations usually observed at Si/SiO2 interfaces and therefore shows very promising results in ionizing environment. Evidence of intrinsically different mechanisms of white pixel formation under irradiation for N-type and P-type pixels have been presented. Finally, back-side illumination technology and the vertical photodiode both contribute to the pixel's high full well capacity and good quantum efficiency
Study of electrical characteristics of tri-gate NMOS transistor in bulk technology by Inga Jolanta Zbierska( )

1 edition published in 2014 in English and held by 1 WorldCat member library worldwide

One of the recent solutions to overcome the scaling limit issue are multi-gate structures. One cost-effective approach is a three-independent-gate NMOSFET fabricated in a standard bulk CMOS process. Apart from their shape, which takes advantage of the three-dimensional space, multi gate transistors are similar to the conventional one. A multi-gate NMOSFET in bulk CMOS process can be fabricated by integration of polysilicon-filled trenches. This trenches are variety of the applications for instance in DRAM memories, power electronics and in image sensors. The image sensors suffer from the parasitic charges between the pixels, called crosstalk. The polysilicon - filled trenches are one of the solution to reduce this phenomenon. These trenches ensure the electrical insulation on the whole matrix pixels. We have investigated its characteristics using l-V measurements, C-V split method and both two- and three-level charge pumping techniques. Tts tunable-threshold and multi-threshold features were verified. Tts surface- channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. We observed no significant degradation of these characteristics due to integration of polysilicon-filled trenches in the CMOS process. The structure has been simulated by using 3D TCAD tool. Tts electrical characteristics has been evaluated and compared with results obtained from electrical measurements. The threshold voltage and the effective channel length were extracted. Tts surface-channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. Owing to the good electrical performances and cost-effective production, we noticed that this device is a good aspirant for analog applications thanks to the multi-threshold voltages
Etude de conception d'ASICs de lecture et d'étiquetage en temps associés à des photomultiplicateurs pour un hodoscope de faisceau en hadronthérapie by Shi-Ming Deng( )

1 edition published in 2012 in French and held by 1 WorldCat member library worldwide

To develop a beam hodoscope in hadrontherapy, able to localize the beam position and to get a time tagging with a accuracy of ~ 1ns at a count rate of 100 000 000 HZ, we have studied and designed read-out ASICs' (Application Specific Intergrated Circuits) to be associated with multi-anode photomultiplier. One of 16-channel front-end ASIC in 0,35 µm AMS BICMOS process ahs been designed, fabraicated and tested. Each channel consists to a current coveyor (with two current outputs) as an input stage, and two separat output stages wich are a current comparator and a charge-sensitive amplifier (CSA) respectively. It performs both signal-event detection and signal charge quantification. The design work includes optimization of circuit performances such as input dynamic range, power dissipation; speed and noise. The circuit has also ben incorporated in a test system and its opration has been verified by beam experimentation. On the other hand, we have also designed another ASIC in a 0.35 µm AMS CMOS process. Itn is based on an analog DLL (Delay Locked Loop) with implementation of the TOF (Time Of Flight) measuring method. It has a LVDS (Low Voltage Differential Signaling) clock input mode and a 5-bit Gray-code output. It operates with 200-ps timing rsolution according to test results. These studies have led us to launch a new design project: integrating the studied and validated electronic functions on a single chip
Étude d'imageurs CMOS fortement dépeuplés pour l'amélioration des performances des futurs instruments d'observation spatiaux by Jean-Baptiste Lincelles( )

1 edition published in 2015 in French and held by 1 WorldCat member library worldwide

This work investigates solutions to extend the space charge region in CMOS image sensors in order to enhance the photo-generatedcharge collection from near-infraredradiations. Photodiode bias increase and low doped silicon substrate are proposed for this study. A theoretical analysis based on analytical model and TCAD simulations shows technological difficulties for photodiode bias in crease and the consequences of using high-resistivity silicon substrates on the imager performances. Space charge region dependency on the pixel design is assessed through simulations. A 3T pixel CMOS image sensor was developed and fabricated on a high resistivity float-zone silicon. Sensor characterization confirms space charge region dependency on the pixel design and the correlation between its extension and electro-optical performances. Design rules are defined to optimize electro-optical performances while limiting punchthrough current in the pixels array
Étude de la réponse dosimétrique du Nitrure de Gallium (GaN) : modélisation, simulation et caractérisation pour la radiothérapie by Ruoxi Wang( )

1 edition published in 2015 in French and held by 1 WorldCat member library worldwide

The work in this thesis has the objective to increase the measurement precision of the dosimetry based on the Gallium Nitride (GaN) transducer and develop its applications on radiotherapy. The study includes the aspects of modeling, simulation and characterization of this response in external radiotherapy and brachytherapy. In modeling, we have proposed two approaches to model the GaN transducer's response in external radiotherapy. For the first approach, a model has been built based on experimental data, while separating the primary and scattering component of the beam. For the second approach, we have adopted a response model initially developed for the silicon diodes for the GaN radioluminescent transducer. We have also proposed an original concept of bi-media dosimetry which evaluates the dose in tissue according to different responses from two media without prior information on the conditions of irradiation. This concept has been shown by Monte Carlo simulation. Moreover, for High Dose Rate brachytherapy, the response of GaN transducer irradiated by iridium 192 and cobalt 60 sources has been evaluated by Monte Carlo simulation and confirmed by the measurements. Studies on the property characterization of GaN radioluminescent transducer has been carried out with these sources as well. An instrumented phantom prototype with GaN probe has been developed for the HDR brachytherapy quality control. It allows a real-time verification of the physics parameters of a treatment (source dwell position, source dwell time, source activity)
Développement et caractérisation de nouveaux procédés de passivation pour les capteurs d'images CMOS by Fatima Zahra Ait Fqir Ali( )

1 edition published in 2013 in French and held by 1 WorldCat member library worldwide

In order to maintain or enhance the electro-optical performances while decreasing the pixel size, advanced CMOS Image Sensors (CIS) requires the implementation of new architectures. For this purpose, deep trenches for pixel isolation (DTI) and backside illumination (BSI) have been introduced as ones of the most promising candidates. The major challenge of these architectures is the high dark current level (Idark) due to the generation/recombination centers present at both, DTI sidewalls and backside surfaces. Therefore, the creation of very shallow doped junctions at these surfaces reducing Idark and further crosstalk by drifting the photo-generated carriers to the photodiode region appears as key process step for introducing these architectures. For the backside surface passivation, a very shallow doped layer can be achieved by low-energy implantation followed by very short and localized heating provided by pulsed laser annealing (PLA). In the melt regime, box-shaped profiles with activation rates close to 100% and excellent crystalline quality have been achieved. The non-melt regime shows some potential, especially for multiple pulse conditions. In the optimal process conditions, very low level of Idark comparable to the standard reference has been achieved. In the other side, the passivation of DTI sidewalls has been performed by in-situ doped Epitaxy. Deposited layers with good uniformity and doping conformity all along the DTI cavity have been achieved. The electrical results show Idark values lower than the standard reference
Développement d'un dispositif intégré de photodétection de grande sensibilité avec discrimination spectrale pour les laboratoires sur puce by Thierry Courcier( )

1 edition published in 2014 in French and held by 1 WorldCat member library worldwide

Ce travail de thèse a pour but de développer un dispositif basé autour d'un dispositif intégré de photodétection pour des applications biomédicales nécessitant une grande sensibilité de détection et une discrimination spectrale (sélectivité). Ce dispositif peut être appliqué, par exemple, à la mesure simultanée de plusieurs marqueurs fluorescents dans les laboratoires sur puce mettant en œuvre de très faibles volumes de réactifs (inférieurs au microlitre). Le travail de thèse se focalise sur la conception, la réalisation et le test de ce dispositif intégré de photodétection. Ce travail se décline selon deux axes principaux : d'une part, la conception d'un photodétecteur CMOS avec préamplificateurs intégrés, et d'autre part la conception, la réalisation et la caractérisation de filtres optiques intégrés performants pour la détection de fluorescence
Developing a method for modeling, characterizing and mitigating parasitic light sensitivity in global shutter CMOS image sensors by Federico Pace( )

1 edition published in 2021 in English and held by 1 WorldCat member library worldwide

L'imagerie à haute-vitesse sans distorsions spatiales est devenue cruciale pour une large gamme d'applications comme la vision industrielle, la reconnaissance du mouvement et l'imagerie de la Terre depuis l'espace. La technologie d'imagerie CMOS a donc évolué vers une modalité de prise de vue appelée « snapshot », grâce au développement des Capteurs d'Image à Obturation Globale. Néanmoins, ce type d'imageurs présente une dégradation des performances due à une sensibilité à la lumière parasite non-négligeable du Nœud de Stockage, qui en limite l'exploitation. Bien que beaucoup de travaux aient été consacrés à la réduction de la Sensibilité à la Lumière Parasite, il existe des interrogations et des manquements relatifs à la caractérisation et la modélisation de cette figure de mérite.Ces travaux s'intéressent au développement d'un cadre pour la modélisation, la caractérisation et l'atténuation de la Sensibilité à la Lumière Parasite dans les imageurs CMOS à Obturation Globale.Le cadre se base sur le développement d'une métrique pour la caractérisation, d'une méthode de simulation et de différentes méthodes de correction en post-traitement dans le but de faire émerger des recommandations pour la conception et d'augmenter les performances des imageurs de manière efficace et peu coûteuse
Étude de la passivation du silicium dans des conditions d'irradiation électronique de faible énergie by Romain Cluzel( )

1 edition published in 2010 in French and held by 1 WorldCat member library worldwide

L'illumination par la face arrière amincie des imageurs CMOS est une des voies étudiées pour accroître le rapport signal à bruit et ainsi la sensibilité de ce capteur. Or cette configuration est adaptée à la détection des électrons dans la gamme d'énergie [[1 ; 12 keV]. L'électron incident crée, par multiplication, plusieurs centaines d'électrons secondaires, proche de la surface. Une couche de passivation par surdopage P++ de la face arrière est nécessaire afin de réduire le nombre de recombinaisons de surface des électrons. Par effet de champ électrique, la couche de passivation augmente le nombre de charges collectées, et ainsi le gain de collection du capteur. L'objectif de cette thèse est de développer des moyens de caractérisation pour déterminer in situ les performances sur le gain de collection de six procédés de passivation. Préalablement, le profil de dépôt d'énergie de l'électron incident est étudié au moyen d'une simulation Monte-Carlo puis d'un modèle analytique. Un modèle associé du gain de collection indique qu'à forte énergie, l'effet miroir de la passivation est déterminant tandis qu'à faible énergie, l'épaisseur de la passivation est un facteur clef. Une première expérience d'irradiation de diodes étendues P++=N permet de dégager l'influence du procédé de passivation sur les recombinaisons de surface. Grâce à une seconde caractérisation de type < événement unique >, directement sur capteur CMOS aminci, les passivations sont discriminées quant à leur effet miroir et l'étalement de la charge qu'elles induisent. Le recuit laser d'activation des dopants peut s'avérer une source d'inhomogénéités du gain sur la surface de la matrice
 
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Languages
French (22)

English (2)